DS2755: High-Accuracy Battery Fuel Gauge with Snapshot

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PMOD

—Sleep Mode Enable. A value of 1 in this bit enables the DS2755 to enter sleep mode when the DQ line

only. The desired default value should be set in bit 5 of address 31h. The factory default is 0.

RNAOP

—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address command

to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should be set in bit 4 of

address 31h. The factory default is 0.

UVEN

—Undervoltage Sleep Enable. A value of 1 in UVEN along with a value of 1 in PMOD enables the DS2755 to

of 0 disables the DS2755 from entering the sleep mode due to undervoltage events. This bit is read-only. The

desired default value should be set in bit 3 of address 31h. The factory default is 0.

IOS

—Interrupt output select. IOS set to a 1 selects the DQ interrupt signaling method. IOS cleared to 0 selects the

PIO interrupt signaling method. The IE bit must be set to enable either type of interrupt. The desired default value

should be set in bit 2 of address 31h. The factory default is 0.

OBEN—

Offset Blanking Enable. A value of 1 in this bit location enables the offset blanking function described in

the Current Accumulation section. If set to 0, the offset blanking function is disabled. This bit is read-only. The

desired default value should be set in bit 1 of address 31h. The factory default is 0.

OVD—

Overdrive Timing Enable. A value of 1 in this bit location enables the Overdrive 1-Wire timings. If set to 0,

the Regular mode timings are enabled. This bit cannot be written directly. The desired bit value must be written to

bit 1 of address 31h, (an EEPROM block 0 location), then recalled before any change to the 1-Wire speed

becomes effective. A power-on reset forces a recall of settings from EEPROM block 0. The factory default in bit 1

of address 31h is 0 (Standard 1-Wire timing).

X

—Reserved Bits.

EEPROM REGISTER

The format of the EEPROM Register is shown in Figure 12. The function of each bit is described in detail in the

following paragraphs.

Figure 12. EEPROM REGISTER FORMAT

Address 07

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EEC

LOCK

X

X

X

BL2

BL1

BL0

EEC

—EEPROM Copy Flag. A 1 in this read-only bit indicates that a Copy Data command is in progress. While this

bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data can be written to unlocked

EEPROM blocks.

LOCK

—EEPROM Lock Enable. When this bit is 0, the Lock command is ignored. Writing a 1 to this bit enables the

Lock command. After the Lock command is executed, the LOCK bit is reset to 0. The factory default is 0.

BL2—

EEPROM Block 2 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 2 (addresses 60 to 7F) is

locked (read-only), while a 0 indicates block 1 is unlocked (read/write).

BL1—

EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses 40 to 5F) is

locked (read-only), while a 0 indicates block 1 is unlocked (read/write).

BL0—

EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses 20 to 3F) is

locked (read-only), while a 0 indicates block 0 is unlocked (read/write).

X

—Reserved Bits.