Data Sheet

ADPA9007

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 7 of 28

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4, 6, 8, 9, 16, 17, 20, 22, 24, 25, 32

GND

Ground. The GND pins must be connected to the RF and the DC ground. See Figure 3 for the

interface schematic.

2, 3, 7, 11, 12, 14, 23, 27, 28, 31

NIC

Not Internally Connected. The NIC pins are not connected internally. However, all data shown

is measured with the NIC pins connected to RF and DC ground externally.

5

RFIN

RF Input of the Amplifier. The RFIN pin is DC-coupled and matched to 50 Ω. See Figure 4 for

the interface schematic.

10

VREF

Reference Diode Voltage for the Temperature Compensation of the VDET RF Output Power

Measurements. The VREF pin voltage (VREF) requires the application of a DC bias voltage

through an external series resistor. See Figure 5 for the interface schematic.

13

VGG1

Gate Control for the Amplifier. Attach bypass capacitors per the Applications Information

section. See the Power-Up Sequence and Power-Down Sequence for additional information.

See Figure 6 for the interface schematic.

15

ACG3

Low Frequency Termination. Attach bypass capacitors per the Applications Information

section. See Figure 4 for the interface schematic.

18

VBTEMP

Temperature Sensor Bias. Bias pin for biasing the integrated temperature sensor. See Figure 7

for the interface schematic.

19

VTEMP

Integrated Temperature Sensor output. See Figure 7 for the interface schematic.

21

RFOUT/VDD RF Output of the Amplifier. Connect the RFOUT/VDD pin to the DC bias (VDD) network to

provide drain current (IDD). See Applications Information section. See Figure 8 for the interface

schematic.

26

VDET

Detector Diode Voltage to Measure the RF Output Power. Detection by the VDET pin

requires the application of a DC bias voltage through an external series resistor. Used in

combination with the VREF pin, the difference detector voltage (VREF − VDET) is a temperature

compensated DC voltage proportional to the RF output power. See Figure 8 for the interface

schematic.

29

ACG2

Low Frequency Termination. Attach bypass capacitors per the Applications Information

section. See Figure 8 for the interface schematic.

30

ACG1

Low Frequency Termination. Attach bypass capacitor per the Applications Information section.

See Figure 8 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and the DC ground.