ADPA9007 datasheet(23/28 Pages) AD

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Data Sheet

ADPA9007

APPLICATIONS INFORMATION

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Rev. 0 | 23 of 28

Figure 84 shows the basic connections for operating the AD-

PA9007. The RFIN and the RFOUT/VDD pins require external

AC-coupling capacitors. The drain bias is applied through a bias

tee on the RFOUT/VDD pin. The nominal drain bias is 15 V.

The negative gate current is applied to the VGG1 pin. A VGG1 of

approximately −0.7 V sets the drain current to 500 mA.

The VDET and VREF pins are connected to 5 V through 40.2 kΩ

biasing resistors to bias internal circuits. Figure 84 shows an option-

al op amp differential amplifier circuit that can be used to subtract

VDET from VREF, yielding a temperature-compensated voltage that

is proportional to the RF output power.

The configuration shown in Figure 84 was used to characterize the

device with the exception of the op-amp circuit. VDET and VREF

were measured at their respective pins with just the two 40.2 kΩ

biasing resistors attached.

Figure 84. Basic Connections

POWER-UP SEQUENCING

The following power-up sequencing in recommended:

1. Connect GND to ground.

2. Set VGG1 to −1.5 V.

3. Set RFOUT/VDD to 15 V.

4. Increase VGG1 to achieve an IDQ = 500 mA.

5. Apply the RF signal.

If the desired gate voltage is known, set the VGG1 directly in Step 2

and skip Step 4.

POWER-DOWN SEQUENCING

The following power-down sequencing is recommended.

1. Turn off the RF signal.

2. Decrease VGG1 to −1.5 V to achieve an IDQ = 0 mA.

3. Decrease VDD to 0 V.

4. Increase VGG1 to 0 V.

ADPA9007 Datasheet(PDF) 23 Page - Analog Devices