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CS4351 Datasheet(PDF) 17 Page - Cirrus Logic |
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CS4351 Datasheet(HTML) 17 Page - Cirrus Logic |
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17 / 37 page ![]() DS566F1 17 CS4351 least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and 36 cycles in format 5. 4.4 De-Emphasis Control The device includes on-chip digital de-emphasis. Figure 8 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Note: De-emphasis is only available in Single-Speed Mode. LR C K SC L K Left C ha nnel Righ t C ha n nel SDIN +3 +2 +1 +5 +4 MSB -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 LSB MSB LSB Figure 5. Left-Justified up to 24-Bit Data LR C K SCL K Left C ha nnel Rig h t Channel SDIN +3 +2 +1 +5 +4 MSB -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 MSB LSB LSB Figure 6. I²S, up to 24-Bit Data LRCK SCLK Left Chan ne l SDIN -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 MSB R ight Cha nne l LSB MSB +1 +2 +3 +4 +5 LSB -6 -5 -4 -3 -2 -1 -7 MSB Figure 7. Right-Justified Data Gain dB -10dB 0dB Frequency T2 = 15 µs T1=50 µs F1 F2 3.183 kHz 10.61 kHz Figure 8. De-Emphasis Curve |
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