CS42448 datasheet(25/64 Pages) CIRRUS

25 / 64 page

DS648F2

CS42448

The ADC output data is in 2’s complement binary format. For inputs above positive full scale or below neg-

ative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow bit

in the register “Status (Address 19h) (Read Only)” on page 51 to be set to a ‘1’.

4.2.2

ADC3 Analog Input

ADC3 accommodates differential as well as single-ended inputs. In Single-Ended Mode, an internal MUX

selects from up to four single-ended inputs.

Single-Ended Mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the

AINx_MUX bits. See register “ADC Control & DAC De-Emphasis (Address 05h)” on page 45 for all bit se-

lections. Refer to Figure 12 on page 27 for the internal ADC3 analog input topology.

Full-Scale Differential Input Level =

(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS

AINx+

AINx-

3.9 V

2.5 V

1.1 V

5.0 V

3.9 V

2.5 V

1.1 V

Figure 10. Full-Scale Input

AIN5

AIN5_MUX

AIN6_MUX

ADC3

Single-Ended Input Filter

Differential

Input Filter

ADC3 SINGLE

Differential

Input Filter

AIN5A

AIN5B

AIN5+/-

AIN6+/-

AIN6A

AIN6B

AIN6

Figure 11. ADC3 Input Topology

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