CS42448 datasheet(27/64 Pages) CIRRUS

27 / 64 page

DS648F2

CS42448

Software Mode

Registers setup to

desired settings.

RST = Low?

No Power

1. VQ = ?

2. Aout bias = ?

3. No audio signal

generated.

Power-Down (Power Applied)

1. VQ = 0 V.

2. Aout = VQ.

3. No audio signal generated.

4. Control Port Registers reset

to default.

Control Port

Active

Control Port

Access Detected?

Hardware Mode not supported.

Codec will power up in an

unknown state once all clocks

and data are valid. It is

recommended that the user

setup up the codec via the

control port before applying

MCLK.

Valid MCLK

Applied?

PDN bit = '1'b?

Sub-Clocks Applied

1. LRCK valid.

2. SCLK valid.

3. Audio samples

processed.

Valid

MCLK/LRCK

Ratio?

Yes

Normal Operation

1. VQ = VA/2.

2. Aout bias = VQ.

3. Audio signal generated per register settings.

Analog Output Freeze

1. VQ = VA/2.

2. Aout bias = VQ + last audio sample.

3. DAC Modulators stop operation.

4. Audible pops.

Analog Output Mute

1. VQ = VA/2.

2. Aout bias = VQ.

3. DAC outputs muted.

4. No audio signal generated.

ERROR: MCLK/LRCK ratio change

ERROR: MCLK removed

RST = Low

PDN bit set

to '1'b

Power-Up Ramp

1. VQ ramp up to VA/2.

2. Aout bias = VQ.

400 ms delay

Power-Down Ramp

1. VQ ramp down to 0 V.

2. Aout bias = VQ.

250 ms delay

Power-Down Mode

1. VQ = 0 V.

2. Aout bias = VQ.

3. No audio signal generated.

4. Control Port Registers retain

settings.

2000 LRCK delay

PopGuard®

Power-Down Transition

1. VQ = 0 V.

2. Aout bias = VQ.

3. Audible pops.

No Power Transition

1. VQ = 0 V.

2. Aout bias = VQ.

3. Audible pops.

ERROR: Power removed

Figure 12. Audio Output Initialization Flow Chart

CS42448 Datasheet(PDF) 27 Page - Cirrus Logic

CS42448 Datasheet(HTML) 27 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL