CS42448 datasheet(37/64 Pages) CIRRUS

37 / 64 page

DS648F2

CS42448

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown

in Figure 25, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-

dition. The following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 10010xx0 (chip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10010xx1(chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each

byte is separated by an acknowledge bit.

4.8

Interrupts

The 42448 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt

input pin on the host microcontroller. The INT pin may be configured as an active low or active high CMOS

driver or an open-drain driver. This last mode is used for active low, wired-OR hook-ups, with multiple pe-

ripherals connected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Status

(Address 19h) (Read Only)” on page 51. Each source may be masked off through mask register bits. In ad-

dition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of

level sensitive or edge sensitive modes within the microcontroller, many different configurations are possi-

ble, depending on the needs of the system designer.

4.9

Recommended Power-Up Sequence

1. Hold RST low until the power supply and clocks are stable. In this state, the control port is reset to its

default settings and VQ will remain low.

SCL

CHIP ADDRESS (WRITE)

MAP BYTE

DATA

DATA +1

START

ACK

STOP

ACK

0 AD1 AD0 0

SDA

0 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR

12 13 14 15

20 21 22 23 24

26 27 28

10 11

17 18

ACK

DATA + n

STOP

Figure 25. Control Port Timing, I²C Read

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