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AD9627PCB Datasheet(PDF) 22 Page - Analog Devices

Part # AD9627PCB
Description  12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
PDF  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9627PCB Datasheet(HTML) 22 Page - Analog Devices

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AD9627
Preliminary Technical Data
Rev. PrA | Page 22 of 40
Gray code when using the SPI control.
Table 3. CLK/DFS Mode Selection (external pin mode)
Voltage at pin
SCLK/DFS
SDIO/DCS
AGND (default)
Binary
DCS Disabled
AVDD
Twos Complement
DCS Enabled
Digital Output Enable Function (OEB)
The AD9627 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled using the
OEB pin or through the SPI interface. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. It is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
When using the SPI interface each channel’s data and fast detect
outputs can be independently three-stated by using the Output
Enable Bar bit in register 0x14.
Figure 21. OR Relation to Input Voltage and Output Data
TIMING
The AD9627 provides latched data with a pipeline delay of
twelve clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9627.
These transients can degrade the converter’s dynamic performance.
The AD9627 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO. See Figure x for a graphical
timing description.
The lowest typical conversion rate of the AD9627 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can
degrade.
Table 4. Output Data Format
Input (V)
Condition (V)
Binary Output Mode
Twos Complement Mode
OR
VIN+ – VIN–
< –VREF – 0.5 LSB
0000 0000 0000
1000 0000 0000
1
VIN+ – VIN–
= –VREF
0000 0000 0000
1000 0000 0000
0
VIN+ – VIN–
= 0
1000 0000 0000
0000 0000 0000
0
VIN+ – VIN–
= +VREF – 1.0 LSB
1111 1111 1111
0111 1111 1111
0
VIN+ – VIN–
> +VREF – 0.5 LSB
1111 1111 1111
0111 1111 1111
1



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