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RT1050 Datasheet(PDF) 39 Page - NXP Semiconductors

Part # RT1050
Description  i.MX RT1050 Crossover Processors Data Sheet for Industrial Products
PDF  115 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

RT1050 Datasheet(HTML) 39 Page - NXP Semiconductors

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Electrical characteristics
i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 2, 03/2021
NXP Semiconductors
39
4.4.2
WDOG reset timing parameters
Figure 8 shows the WDOG reset timing and Table 29 lists the timing parameters.
Figure 8. WDOGn_B timing diagram
NOTE
RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or
approximately 30
s.
NOTE
WDOGn_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
4.4.3
SCAN JTAG Controller (SJC) timing parameters
Figure 9 depicts the SJC test clock input timing. Figure 10 depicts the SJC boundary scan timing.
Figure 11 depicts the SJC test access port. Signal parameters are listed in Table 30.
Figure 9. Test clock input timing diagram
Table 29. WDOGn_B timing parameters
ID
Parameter
Min
Max
Unit
CC3
Duration of WDOGn_B Assertion
1
—
RTC_XTALI cycle
WDOGn_B
CC3
(Output)
JTAG_TCK
(Input)
VM
VM
VIH
VIL
SJ1
SJ2
SJ2
SJ3
SJ3



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