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PM5366-PI Datasheet(PDF) 248 Page - PMC-Sierra, Inc |
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PM5366-PI Datasheet(HTML) 248 Page - PMC-Sierra, Inc |
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248 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 236 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 4. Maximum and minimum output propagation delays are measured with a 50 pF load on all the outputs. Table 45 - Line Side Telecom Bus Input Timing – 19.44 MHz (Figure 67) Symbol Description Min Max Units LREFCLK Frequency 19.44 -50 ppm 19.44 +50 ppm MHz LREFCLK Duty Cycle 40 60 % LREFCLK skew relative to SREFCLK -10 10 ns CLK52M Frequency (51.84 MHz) 51.84 -50 ppm 51.84 +50 ppm MHz CLK52M Frequency (44.928 MHz) 44.928 -50 ppm 44.928 +50 ppm MHz CLK52M Duty Cycle 40 60 % tSTEL All Telecom BUS Inputs Set-Up Time to LREFCLK 5ns THTEL All Telecom BUS Inputs Hold Time to LREFCLK 1ns Line Side Telecom Bus Input Timing - 77.76 MHz (Figure 67) Symbol Description Min Max Units LREFCLK Frequency 77.76 -50 ppm 77.76 +50 ppm MHz LREFCLK Duty Cycle 40 60 % LREFCLK skew relative to SREFCLK -5 5 ns |
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