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PM5366-PI Datasheet(PDF) 41 Page - PMC-Sierra, Inc

Part # PM5366-PI
Description  HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
PDF  267 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 41 Page - PMC-Sierra, Inc

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PRELIMINARY
PM5366 TEMAP-84
DATASHEET
PMC-2010672
ISSUE 1
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
29
Pin Name
Type
Pin
No.
Function
TPOS/TDAT[3]
TPOS/TDAT[2]
TPOS/TDAT[1]
Output R2
U2
AA1
Transmit Positive Pulse (TPOS[3:1]). TPOS[3:1]
represent the positive pulses transmitted on the B3ZS-
encoded DS3 or HDB3-encoded E3 lines when dual-
rail output format is selected.
Transmit Data Output (TDAT[3:1]). TDAT[3:1]
represent the NRZ (unipolar) DS3 output data streams
when single rail output format is selected.
TPOS[3:1] and TDAT[3:1] are updated on the falling
edge of the associated TCLK by default but may be
enabled to be updated on the rising edge of the
associated TCLK by setting the TRISE bit in the
DS3/E3 Master Transmit Line Options register.
TPOS[3:1] and TDAT[3:1] are updated on TICLK[3:1]
rather than TCLK[3:1] when the TICLK bit in the
DS3/E3 Master Transmit Line Options register is set.
TNEG/TMFP[3]
TNEG/TMFP[2]
TNEG/TMFP[1]
Output U4
W1
AB1
Transmit Negative Pulse (TNEG[3:1]). TNEG[3:1]
represent the negative pulses transmitted on the
B3ZS-encoded DS3 or HDB3-encoded E3 lines when
dual-rail output format is selected.
Transmit Multiframe Pulse (TMFP[3:1]). These
signals mark the transmit frame alignment when
configured for single rail operation. TMFP[3:1] indicate
the position of overhead bits in the transmit
transmission system stream, TDAT[3:1]. TMFP[3:1]
are high during the first bit (X1) of the multiframe or E3
frame.
TNEG[3:1] and TMFP[3:1] are updated on the falling
edge of the associated TCLK by default but may be
enabled to be updated on the rising edge of the
associated TCLK by setting the TRISE bit in the
DS3/E3 Master Transmit Line Options register.
TNEG[3:1] and TMFP[3:1] are updated on TICLK[3:1]
rather than TCLK[3:1] when the TICLK bit in the
DS3/E3 Master Transmit Line Options register is set.
TICLK[3]
TICLK[2]
TICLK[1]
Input
T4
V4
Y2
Transmit input clock (TICLK[3:1]). TICLK[3:1]
provides the transmit direction timing for the three
DS3s or E3s. TICLK[3:1] are nominally 44.736 MHz or
34.368 MHz, 50% duty cycle clocks.



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