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PM5366-PI Datasheet(PDF) 50 Page - PMC-Sierra, Inc

Part # PM5366-PI
Description  HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
PDF  267 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 50 Page - PMC-Sierra, Inc

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PRELIMINARY
PM5366 TEMAP-84
DATASHEET
PMC-2010672
ISSUE 1
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
38
Pin Name
Type
Pin
No.
Function
L77
Input
AA4 The Line 77.76 MHz select input determines the
expected frequency of LREFCLK. If L77 is low,
LREFCLK is expected to be 19.44 MHz. If L77 is high,
LREFCLK is expected to be 77.76 MHz and data is
driven and sampled every fourth cycle.
L77 must be held static.
LAC1
Input
W10 Line Add C1 Frame Pulse (LAC1). The Add bus
timing signal identifies the frame and multiframe
boundaries on the Add Data bus LADATA[7:0].
LAC1 is set high to mark the first C1 byte of the first
transport envelope frame of the 4 frame multiframe on
the LADATA[7:0] bus. LAC1 need not be presented on
every occurrence of the multiframe .
LAC1 is sampled on the rising edge of LREFCLK.
LAC1J1V1
Output AA11 Line Add Bus Composite Timing Signal
(LAC1J1V1). The Add bus composite timing signal
identifies the frame, payload and tributary multiframe
boundaries on the Line Add Data bus LADATA[7:0].
LAC1J1V1 pulses high with the Line Add Payload
Active signal LAPL set low to mark the first STS-1
(STM-0/AU3) identification byte or equivalently the
STM identification byte C1. Optionally the LAC1J1V1
signal pulses high with LAPL set high to mark the path
trace byte J1. Optionally the LAC1J1V1 signal pulses
high on the V1 byte to indicate tributary multiframe
boundaries.
In a system with multiple TEMAP-84s sharing the
same Line Add bus only one device should have
LAC1J1V1 connected. All devices must be configured
via the TXPTR[9:0] bits in the SONET/SDH Transmit
Pointer Configuration and TTMP Telecom Interface
Configuration registers for the same J1 location.
When L77 high, LAC1J1V1 is only valid (i.e. identifies
the first C1, J1 and V1 of the concatenated STM-4
data stream) if the LSTM[1:0] bits in the Master Bus
Configuration register (0x0006) are set to “00”.
LAC1J1V1 is updated on the rising edge of LREFCLK.



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