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PM5366-PI Datasheet(PDF) 40 Page - PMC-Sierra, Inc |
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PM5366-PI Datasheet(HTML) 40 Page - PMC-Sierra, Inc |
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40 / 267 page ![]() PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 28 8 PIN DESCRIPTION Pin Name Type Pin No. Function DS3 and E3 Line Side Interface RCLK[3] RCLK[2] RCLK[1] Input P1 T1 Y1 Receive Input Clocks (RCLK[3:1]). RCLK[3:1] provide the receive direction timing for the three DS3s or E3s. RCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clock inputs. RPOS/RDAT[3] RPOS/RDAT[2] RPOS/RDAT[1] Input P2 U1 V3 Positive Input Pulse (RPOS[3:1]). RPOS[3:1] represent the positive pulses received on the B3ZS- encoded DS3s or HDB3-encoded E3s when dual rail input format is selected. Receive Data Input (RDAT[3:1]). RDAT[3:1] represent the NRZ (unipolar) DS3 or E3 input data streams when single rail input format is selected. RPOS[3:1] and RDAT[3:1] are sampled on the rising edge of the associated RCLK by default and may be enabled to be sampled on the falling edge of the associated RCLK by setting the RFALL bit in the DS3/E3 Master Receive Line Options register. RNEG/RLCV[3] RNEG/RLCV[2] RNEG/RLCV[1] Input P3 T3 W2 Negative Input Pulse (RNEG[3:1]). RNEG[3:1] represent the negative pulses received on the B3ZS- encoded DS3s or HDB3-encoded E3s when dual rail input format is selected. Line code violation (RLCV[3:1]). RLCV[3:1] represent receive line code violations when single rail input format is selected. RNEG[3:1] and RLCV[3:1] are sampled on the rising edge of the associated RCLK by default and may be enabled to be sampled on the falling edge of RCLK by setting the RFALL bit in the DS3/E3 Master Receive Line Options register. TCLK[3] TCLK[2] TCLK[1] Output R3 V1 W3 Transmit Clock (TCLK[3:1]). TCLK[3:1] provide timing for circuitry downstream of the DS3 and E3 transmitters of the TEMAP-84. TCLK[3:1] are nominally 44.736 MHz or 34.368 MHz, 50% duty cycle clocks. |
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