LM5177 datasheet(6/112 Pages) TI

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Table 5-1. Pin Functions (continued)

I/O(1)

DESCRIPTION

NAME

NO.

ILIMCOMP/ISET

Compensation pin for average current limit loop. Connect an capacitor or a type 2 R-C

network if the current limit is set by the internal DAC.

If the internal DAC is disabled the pin sets the current limit threshold for the average current

limit. Connect a resistor to AGND. A parallel filter of capacitor is recommended depending

on the application requirements

Connect a resistor to AGND if the current limit is set by ISET.

Connect the ISET pin to VCC2 to disable the block and reduce the quiescent current

AGND

Analog Ground

VOUT

Output voltage sense input. Connect to the power stage output rail.

ISNSN

Negative sense input of the output or input average current sense amplifier. An optional

current sense resistor connected between ISNSN and ISNSP can be located either on the

input side or on the output side of the power stage.

In case the optional current sensor is disabled connect ISNSN and ISNSP together to

AGND

ISNSP

Positive sense input of the output or input current sense amplifier. An optional current sense

resistor connected between ISNSN and ISNSP can be placed either on the input side or on

the output side of the power stage.

In case the optional current sensor is disabled connect ISNSP to ground

CSB

Inductor peak current sense negative input. Connect CSB to the negative side of the

external current sense resistor using a Kelvin connection.

CSA

Inductor peak current sense positive input. Connect CSA to the positive side of the external

current sense resistor using a Kelvin connection.

SW1

Inductor switch node for the buck half-bridge

HO1

High-side gate driver output for the buck half-bridge

HB1

Bootstrap supply pin for buck half-bridge. An external capacitor is required between the HB1

pin and the SW1 pin, to provide bias to the high-side MOSFET gate driver.

Place the external capacitor close to the pin without any resistance between the pin and

capacitor for good decoupling

Not Connected

LO1

Low-side gate driver output for the buck half-bridge

PGND

Power Ground

VCC2

Internal linear bias regulator output. Connect a ceramic decoupling capacitor from VCC to

PGND. This rail supplies the internal logic and the gate driver.

Place the external capacitor close to the pin without any resistance between the pin and

capacitor for good decoupling.

LO2

Low-side gate driver output for the boost half-bridge

HB2

Bootstrap supply pin for boost half-bridge. An external capacitor is required between the

HB2 pin and the SW2 pin, to provide bias to the high-side MOSFET gate driver

Place the external capacitor close to the pin without any resistance between the pin and

capacitor for good decoupling

HO2

High-side gate driver output for the boost half-bridge

SW2

Inductor switch node for the buck half-bridge

Not Connected

DRV1

External FET drive pin. This pin features a high-voltage push pull stage, a open drain output

or a charge pump driver stage according to the selected configuration.

In case the optional DRV pin is not used you can leave DRV open.

VIN

The input supply and sense input of the device. Connect VIN to the supply voltage of the

power stage.

LM251772

SNVSCT9 – OCTOBER 2024

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