PM7366-PI datasheet(233/286 Pages) PMC

233 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

220

be reset, but not set. A bit is reset whenever the register is written, and the data in the

corresponding bit location is a one.

FBTBE:

The FBTBE bit is hardwired to one to indicate the GPIC supports fast back-to-back

transactions with other targets.

DPR:

The Data Parity Reported (DPR) bit is set high if the GPIC is an initiator and asserts or

detects a parity error on the PERRB signal while the PERREN bit is set in the Command

DVSLT[1:0]:

The Device Select Timing (DEVSLT) bits specify the allowable timings for the assertion of

DEVSELB by the GPIC as a target. These are encoded as 00B for fast, 01B for medium, 10B

for slow and 11B is not used. The GPIC allows for medium timing.

TABT:

The Target Abort (TABT) bit is set high by the GPIC when as a target, it terminates a

transaction with a target abort. The TABT bit is cleared by the PCI Host.

RTABT:

The Received Target Abort (RTABT) bit is set high by the GPIC when as an initiator, its

transaction is terminated by a target abort. The RTABT bit is cleared by the PCI Host.

MABT:

The Master Abort (MABT) bit is set high by the GPIC when as an initiator, its transaction is

terminated by a master abort and a special cycle was not in progress. The MABT bit is

cleared by the PCI Host.

SERR:

The System Error (SERR) bit is set high whenever the GPIC asserts the SERRB output. The

SERR bit is cleared by the PCI Host.

PERR:

The Parity Error (PERR) bit is set high whenever the GPIC detects a parity error, even if parity

error handling is disabled by clearing PERREN in the Command register. The PERR bit is

cleared by the PCI Host.

PM7366-PI Datasheet(PDF) 233 Page - PMC-Sierra, Inc