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MAX7321 Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX7321 Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 17 page ![]() Slave Address and Input Pullup Selection Address inputs AD0 and AD2 determine the MAX7323 slave address, select which inputs have pullup resis- tors, and set the default logic state on outputs. Pullups are enabled on the input ports in groups of two (see Table 3). The MAX7319, MAX7321, MAX7322, and MAX7323 use a different range of slave addresses (110xxxx) than the MAX7320 (101xxxx). The MAX7323 slave address is determined on each I2C transmission, regardless of whether the transmission is actually addressing the MAX7323. The MAX7323 distin- guishes whether address inputs AD2 and AD0 are con- nected to SDA or SCL instead of fixed logic levels V+ or GND during this transmission. Therefore, the MAX7323 slave address can be configured dynamical- ly in the application without cycling the device supply. On initial power-up, the MAX7323 cannot decode address inputs AD2 and AD0 fully until the first I2C transmission. AD0 and AD2 initially appear to be con- nected to V+ or GND. This is important because the address selection determines the power-up default states of the output ports and I/O port initial logic state, and whether pullups are enabled. However, at power- up, the I2C SDA and SCL bus interface lines are high impedance at the pins of every device (master or slave) connected to the bus, including the MAX7323. This is guaranteed as part of the I2C specification. Therefore, address inputs AD2 and AD0 that are connected to SDA or SCL normally appear at power-up to be con- nected to V+. The pullup selection logic uses AD0 to select whether pullups are enabled for ports P2 and P3, and to set the initial logic state for O0 and O1. AD2 selects whether pullups are enabled for ports P4 and P5 and sets the initial logic state for O6 and O7. The rule is that a logic-high, SDA, or SCL connection selects the pullups and sets the default logic state to high. A logic-low deselects the pullups and sets the default logic state low (see Table 3). The port configu- ration is correct on power-up for a standard I2C config- uration, where SDA or SCL are pulled up to V+ by the external I2C pullup resistors. There are circumstances where the assumption that SDA = SCL = V+ on power-up is not true—for example, in applications in which there is legitimate bus activity during power-up. Also, if SDA and SCL are terminated with pullup resistors to a different supply voltage than the MAX7323’s supply voltage, and if that pullup supply rises later than the MAX7323’s supply, then SDA or SCL may appear at power-up to be connected to GND. In such applications, use the four address combina- tions that are selected by connecting address inputs I2C Port Expander with 4 Push-Pull Outputs and 4 Open-Drain I/Os _______________________________________________________________________________________ 7 PART I2C SLAVE ADDRESS INPUTS INTERRUPT MASK OPEN- DRAIN OUTPUTS PUSH- PULL OUTPUTS I2C DATA WRITE I2C DATA READ MAX7319 110xxxx 8 Yes — — <I7–I0 interrupt mask> <I7–I0 port inputs> <I7–I0 transition flags> MAX7320 101xxxx —— — 8 <O7–O0 port outputs> <O7-O0 port inputs> MAX7321 110xxxx Up to 8 — Up to 8 — <P7–P0 port outputs> <P7–P0 port inputs> <P7–P0 transition flags> MAX7322 110xxxx 4 Yes — 4 <O7, O6 outputs, I5–I2 interrupt mask, O1, O0 outputs> <O7, O6, I5–I2, O1, O0 port inputs> <0, 0, I5–I2 transition flags, 0, 0> MAX7323 110xxxx Up to 4 — Up to 4 4 <port outputs> <O7, O6, P5–P2, O1, O0 port inputs> <0, 0, P5–P2 transition flags, 0, 0> MAX7328 0100xxx Up to 8 — Up to 8 — <P7–P0 port outputs> <P7–P0 port inputs> MAX7329 0111xxx Up to 8 — Up to 8 — <P7–P0 port outputs> <P7–P0 port inputs> Table 2. Read and Write Access to Eight-Port Expander Family |
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