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MCP16501 Datasheet(PDF) 25 Page - Microchip Technology

Part # MCP16501
Description  Cost and Size Optimized PMIC for SAMA5DX/SAM9X6/SAM9X7/SAMA7G Series MPUs
PDF  42 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP16501 Datasheet(HTML) 25 Page - Microchip Technology

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 2020-2022 Microchip Technology Inc. and its subsidiaries
DS20006388E-page 25
MCP16501
4.4.6
RESTART SEQUENCE AFTER
FAULT AND AUTOMATIC WAKE-UP
PULSE (AWKP)
GENERATION-MCP16501D ONLY
Due to the support for LPDDRx, which require correct
sequencing between the LPDDRx memory rails, the
MCP16501D features a different Fault management
sequence. The correct Fault management sequence
consists in the turn-off of all channels followed by an
automatically executed restart sequence, which
ensures that the power rails will be restarted in the
correct order.
See Section 5.5 “Protections” for information on
which Faults may trigger a new restart sequence. In the
default configuration of the MCP16501D as soon as a
Fault is detected, the power delivery on all channels is
terminated and the MCP16501D waits for 100 ms. After
this wait time, a new start-up sequence is generated in
the attempt to restart the system correctly.
A special feature is provided to enable system recovery
if there is a restart sequence after a Fault occurs while
in Hibernate mode. In Hibernate mode, the PWRHLD
had been previously set to low by the MPU and the
MPU expects a wake-up event in order to set PWRHLD
to high again. This must be a hardware event which is
flagged to some I/O inside the MPU Shutdown and
Wake-up Controller (SHDWC) block (e.g., a logic
transition on a WKUPx or PIOBUx pin).
However, if a Fault causes a restart sequence while in
Hibernate mode, the restart sequence is not success-
fully completed until a wake-up event is generated for
the MPU SHDWC, because the PWRHLD remains low.
It is necessary for the PWRHLD signal to be high just
prior to the completion of the start-up sequence so that
nRSTO can be deasserted. This is solved by generat-
ing from the MCP16501 an Automatic Wake-up Pulse
(AWKP) on the nSTRTO output if the Fault that gener-
ates a restart sequence has occurred while in Hiber-
nate mode.
In the MCP16501D, the AWKP function is enabled by
default.
The timing diagram of a restart sequence caused by a
Fault while in Hibernate mode is shown in Figure 4-10.
Just before initiating the restart sequence, the
MCP16501D generates a 25 ms (nominal duration)
Automatic Wake-up Pulse on the nSTRTO output, even
in lack of a low level on the nSTRT input. This is the
only situation where the nSTRTO logic level does not
reflect the nSTRT input status. The duration of the
AWK Pulse erodes into the 100 ms waiting time that
precedes the automatic restart sequence.
PWRHLD will typically return high as soon as the
nSTRTO signal is detected to be low by the MPU
SHDWC. If LPM stays high for any reason, the
MCP16501D will go in Low-Power mode immediately
after the automatic start-up sequence. This behavior is
shown in Figure 2-21 in Section 2.0 “Typical Perfor-
mance Curves”.
If the restart sequence after a Fault is executed in any
other operational state but Hibernate, PWRHLD will
either be already high (in applications with backup
power) or it would return high as soon as the VDDIO rail
is started, thus making the generation of the Automatic
Wake-up Pulse not necessary.
FIGURE 4-10:
Automatic Wake-Up Pulse
Generation Timing Diagram (Fault during
Hibernate).
VIN
Fault
Event
PWRHLD
Wait 100 ms
(internal logic signal)
nSTRTO
nRSTO
time
LPM
Hibernate
Automatic Start-up Sequence
State
nSTRT
25 ms
100 ms
Wait after Fault
ACTIVE
75 ms
t
restart
t
5
t
5
Where:
trestart = Duration of the automatic start-up
(restart) sequence
t5 = Minimum setup/hold time: Min. 0 µs
(internal filtering applies)



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