MCP16501 datasheet(15/42 Pages) MICROCHIP

15 / 42 page

 2020-2022 Microchip Technology Inc. and its subsidiaries

DS20006388E-page 15

MCP16501

4.0

DEVICE OPTIONS

The MCP16501 is offered in different options,

depending on the target I/O voltage needed external

memory type and behavior in bypass situations.

Table 4-1 shows the device options that are currently

available.

4.1

Buck Channels and Related

External Components

The MCP16501 Buck channels are based on Peak

Current mode control architecture and have internal

frequency compensation for the voltage regulation

loop. The slope compensation is optimized for

inductors in the 1.5 µH to 2.2 µH range. A minimum

output capacitor of 22 µF is required for stability.

Output capacitance can be increased if necessary;

however, it is recommended that the maximum output

capacitance value be limited to avoid engaging the

Hiccup mode overcurrent protection during the initial

soft start ramp. Further details are given in

Section 5.6 “Maximum Simultaneous Capacitive

and DC Loading in Soft Start”.

The recommended input decoupling capacitance on

each Buck channel is 4.7 µF.

The Buck channels can operate in either Forced PWM

mode (Continuous Inductor Current mode), where the

inductor current is allowed to go negative, or in Auto-

matic PFM mode, where the inductor current is

prevented from going negative through Zero-Current

Detection (ZCD) and diode emulation of the low-side

MOSFET.

The switching frequency in Forced PWM mode is

nominally 2 MHz.

4.2

LDO Channel and Related

External Components

The MCP16501 LDO is designed for operation with

low-ESR ceramic output capacitors of 2.2 µF (minimum

value) for loads up to 150 mA, and of 4.7 µF (minimum

value) for loads up to 300 mA. The total output

capacitance must not exceed 20 µF. Recommended

capacitor part numbers are given in Section 5.1

“Recommended External Components”.

4.3

Control Signals and Power States

4.3.1

INTERFACING SIGNALS

The MCP16501 is interfaced to the host MPU by means

of the following signals: nSTRTO (open-drain output),

nRSTO (open-drain output), PWRHLD (input) and LPM

(input).The ESD protection on each interfacing signal is

purposely designed to prevent any leakage from the

MPU I/Os, even in the case where the main input power

is removed from the MCP16501.

Note:

All device variants are generated at the

factory

with

One-Time-Programmable

memory, which configures default settings

at power-up. Contact your nearest

Microchip

Sales

Office

for

further

assistance

the

development

customized device variants.

TABLE 4-1:

DEFAULT CONFIGURATIONS

Device Options

MCP16501A

MCP16501B

MCP16501C

MCP16501D

MCP16501E

VOUT1

3.3V

2.8V

3.3V

LPDDR2/3

Not supported

Supported

Not supported

Hysteretic Control

Mode (HCM)

Not supported

Supported

MCP16501 Datasheet(PDF) 15 Page - Microchip Technology

MCP16501 Datasheet(HTML) 15 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL