RM5231 datasheet(11/39 Pages) PMC

11 / 39 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002165, Issue 1

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

Hardware Overview

The RM5231 offers a high-level of integration targeted at high-performance embedded

applications. The key elements of the RM5231 are briefly described in this section.

3.1

Superscalar Dispatch

The RM5231 has an asymmetric superscalar dispatch unit which allows it to issue an integer

instruction and a floating-point computation instruction simultaneously. Integer instructions

include ALU, branch, load/store, and floating-point load/store, while floating-point computation

instructions include floating-point add, subtract, combined multiply-add, converts, etc. In

combination with its high-throughput fully pipelined floating-point execution unit, the superscalar

capability of the RM5231 provides unparalleled price/performance in computationally intensive

embedded applications.

3.2

CPU Registers

The RM5231 CPU has a user-visible state consisting of 32 general purpose registers, two special

purpose registers for integer multiplication and division, a program counter, and no condition code

bits. Figure 2 shows the user visible state.

Figure 2 CPU Registers

3.3

Pipeline

For integer operations, loads, stores, and other non-floating-point operations, the RM5231 uses a

5-stage pipeline. In addition to the integer pipeline, the RM5231 uses an extended 7-stage pipeline

for floating-point operations.

Figure 3 shows the RM5231 integer pipeline. As illustrated in the figure, up to five integer

instructions can be executing simultaneously.

General Purpose Registers

Multiply/Divide Registers

•

Program Counter

•

r29

r30

r31

RM5231 Datasheet(PDF) 11 Page - PMC-Sierra, Inc