RM5231 datasheet(12/39 Pages) PMC

12 / 39 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002165, Issue 1

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

Figure 3 Pipeline

3.4

Integer Unit

The RM5231 integer unit includes thirty-two general purpose 64-bit registers, a load/store

architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous

multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-

operand integer multiply/divide operations, and the program counter (PC).

The RM5231 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward

compatible with applications that run on processors implementing the earlier generation MIPS I-

III instruction sets.

3.5

The RM5231 has thirty-two general purpose registers with register location 0 (r0) hard wired to a

zero value. These registers are used for scalar integer operations and address calculation. The

latency in the pipeline.

3.6

ALU

The RM5231 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder

performs address calculations in addition to arithmetic operations. The logic unit performs all

logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each

of these units is optimized to perform all operations in a single processor cycle.

3.7

Integer Multiply/Divide

The RM5231 has a dedicated integer multiply/divide unit optimized for high-speed multiply and

multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on

each operation.

one cycle

1I-1R:

2I:

2A-2D:

2R:

1A-2A:

1A:

1D:

2A:

2W:

Instruction cache access

Instruction virtual to physical address translation

Issue or slip decision, Branch decision

Integer add, logical, shift

Data virtual address calculation

Data virtual to physical address translation

Store Align

Data cache access and load align

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