KSZ8565R datasheet(63/235 Pages) MICROCHIP

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DS00002327F-page 63

KSZ8565R

4.13.2

REDUCED MEDIA INDEPENDENT INTERFACE (RMII)

The reduced media independent interface (RMII) specifies a low pin count interface, which is based on MII, that provides

communication with a MAC attached to the port. As with MII, RMII provides a common interface between physical layer

and MAC layer devices, or between two MAC layer devices, and has the following key characteristics:

• Supports network data rates of either 10Mbps or 100Mbps.

• Uses a single 50MHz clock reference (provided internally or externally) for both transmit and receive data.

• Uses independent 2-bit wide transmit and receive data paths.

• Contains two distinct groups of signals: one for transmission and the other for reception.

The user selects one of the two RMII clocking modes by setting the appropriate strapping option.

While in RMII Normal Mode, the port will require an external 50MHz signal to be input to TX_CLK/REFCLKI from an

external source. This mode is selected by strapping the pin RXD1 high during reset.

While in RMII Clock Mode, the port will output a 50MHz clock on RX_CLK/REFCLKO, which is derived from the 25MHz

crystal or oscillator attached to the XI clock input. The TX_CLK/REFCLKI input is unused in this mode. This mode is

selected by strapping the pin RXD1 low during reset.

Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional configuration strap information.

Table 4-31 describes the signals used by the RMII interface. Refer to the RMII specification for full details on the signal

descriptions.

Port 5 in RMII mode may connect to either an external MAC device (such as a host processor) or to an external PHY;

but unlike MII, RMII does not provide separate PHY and MAC modes of operation. However, it is necessary to connect

the pins properly.

Receive Data Bits [3:0]

TXD[3:0] (input)

RXD[3:0] (output)

Receive Clock

TX_CLK (input)

RX_CLK (output)

TABLE 4-31:

RMII SIGNAL DESCRIPTIONS

RMII Signal

Name

(per spec)

RMII Signal

(per KSZ8565R)

Pin Direction

(with respect to

PHY, KSZ8565R)

Pin Direction

(with respect to

MAC)

RMII Signal Description

REF_CLK

REFCLKI

Input

Input or Output

Synchronous 50MHz reference clock,

when port is in RMII Normal Mode

n/a

REFCLKO

Output

Input

Synchronous 50MHz reference clock,

when port is in RMII Clock Mode

TX_EN

Input

Output

Transmit Enable

TXD[1:0]

Input

Output

Transmit Data Bit [1:0]

CRS_DV

RX_DV

Output

Input

Carrier Sense / Receive Data Valid

RX_ER

Output

Input or

not required

Receive Error

RXD[1:0]

Output

Input

Receive Data Bit [1:0]

TABLE 4-30:

MII (MAC MODE) CONNECTION TO EXTERNAL PHY (CONTINUED)

MII Interface Signals Description

KSZ8565R Signals in MAC Mode

External PHY Device Signals

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