KSZ8565R datasheet(64/235 Pages) MICROCHIP

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KSZ8565R

DS00002327F-page 64

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4.13.3

REDUCED GIGABIT MEDIA INDEPENDENT INTERFACE (RGMII)

RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:

• Pin count is reduced from 24 pins for GMII to 12 pins for RGMII.

• All speeds (10Mbps, 100Mbps and 1000Mbps) are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each four bits wide - a nibble.

In RGMII operation, the RGMII pins function as follows:

• The MAC sources the transmit reference clock, TX_CLK, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and

2.5MHz for 10Mbps.

• The PHY recovers and sources the receive reference clock, RX_CLK, at 125MHz for 1000Mbps, 25MHz for

100Mbps, and 2.5MHz for 10Mbps.

• For 1000BASE-T, the transmit data, TXD[3:0], is presented on both edges of TX_CLK, and the received data,

RXD[3:0], is clocked out on both edges of the recovered 125MHz clock, RX_CLK.

• For 10BASE-T/100BASE-TX, the MAC holds TX_CTL low until both the PHY and MAC operate at the same

speed. During the speed transition, the receive clock is stretched on either a positive of neagative pulse to ensure

that no clock glitch is presented to the MAC.

• TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These

two RGMII control signals are valid at the falling clock edge.

After power-up or reset, the device is configured to RGMII mode if the appropriate configuration strap pins are set to

one of the RGMII mode capability options. Refer to Section 3.2.1, "Configuration Straps," on page 16 for available

options. Note that there is no mechanism for the RGMII interface to adapt its speed automatically to the speed of the

connected RGMII device. A configuration strap option sets the speed of the RGMII interface at power-up to either

1000Mbps or 100Mbps. A control register can override the configuration strap option and set the RGMII speed to either

1000, 100 or 10Mbps. If a PHY is connected to the RGMII port, it should be ensured that the PHY link speed is fixed in

order to avoid a mismatch to the RGMII speed.

TABLE 4-32:

RMII CONNECTION TO EXTERNAL MAC

RMII Interface Signals Description

KSZ8565R Signals

External MAC Device Signals

Transmit Enable

TX_EN (input)

TX_EN (output)

Transmit Data Bits [1:0]

TXD[1:0] (input)

TXD[1:0] (output)

Reference Clock

REFCLKI (input)

or REFCLKO (output)

REF_CLK

(input or output)

Carrier Sense Data Valid

RX_DV (output)

CRS_DV (input)

Receive Error

RX_ER (output)

RX_ER (input)

Receive Data Bits [1:0]

RXD[1:0] (output)

RXD[1:0] (input)

TABLE 4-33:

RMII CONNECTION TO EXTERNAL PHY

RMII Interface Signals Description

KSZ8565R Signals

External PHY Device Signals

Transmit Enable

RX_DV (output)

TX_EN (input)

Transmit Data Bits [1:0]

RXD[1:0] (output)

TXD[1:0] (input)

Reference Clock

REFCLKI (input)

or REFCLKO (output)

REF_CLK

(input or output)

Carrier Sense Data Valid

TX_EN (input)

CRS_DV (output)

Receive Error

No connection

RX_ER (output)

Receive Data Bits [1:0]

TXD[1:0] (input)

RXD[1:0] (output)

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