8.2.2 Detailed Design Procedure

1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the

device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout

section.

2. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will optimize

performance. This can be accomplished by providing short, appropriately sized traces from the SN74AC596

to one or more of the receiving devices.

3. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum

output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive

load measured in MΩ; much larger than the minimum calculated previously.

4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

8.2.3 Application Curves

GPO

EN

VCC

V

O

Figure 8-2. Typical Application Timing Diagram

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the

Recommended Operating Conditions.

Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For the SN74AC596, a

0.1μF bypass capacitor is recommended. To reject different frequencies of noise, use multiple bypass capacitors

in parallel. Capacitors with values of 0.1μF and 1μF are commonly used in parallel.

8.4 Layout

8.4.1 Layout Guidelines

• Bypass capacitor placement

– Place near the positive supply terminal of the device

– Provide an electrically short ground return path

– Use wide traces to minimize impedance

– Keep the device, capacitors, and traces on the same side of the board whenever possible

• Signal trace geometry

– 8mil to 12mil trace width

– Lengths less than 12cm to minimize transmission line effects

– Avoid 90° corners for signal traces

– Use an unbroken ground plane below signal traces

– Flood fill areas around signal traces with ground

– For traces longer than 12cm

• Use impedance controlled traces

• Source-terminate using a series damping resistor near the output

• Avoid branches; buffer signals that must branch separately

SN74AC3G99

SCASE46 – NOVEMBER 2024

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