YDA136

16

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DAC Function

YDA136 has a 24-bit×2ch of DAC.

The DAC supports the following eight kinds of sampling frequencies (Fs), and it has an over sampling filter corresponding

to each sampling frequencies.

32kHz、44.1kHz、48kHz、64kHz、88.4kHz、96kHz、176.4kHz、192kHz

The output full-scale of this DAC is 1Vrms.

●DAC Interface

Be sure to input a digital audio signal from the following three terminals, SDIN, LRCLK, and SCLK.

DAC interface of YDA136 supports the seven DAC input formats.

Be sure to set up control registers, MOD2, MOD1, and MOD0, and then select a DAC input format to use.

When using the YDA136 as Digital Audio Signal mode, be sure not to stop a SCLK signal except when electronic volume

is mute, protection reset mode, or hard mute mode.

MODE4(16bit) MODE5(20bit) MODE6(24bit)

MODE7

DAC Input Format

MODE8

Analog Audio Signal Input Mode

MSB

LSB

MSB

LSB

SCLK

LRCLK

SDIN

X

X

Left channel

Right channel

A SDIN bit is sampled by the rising edge of SCLK.

When LRCLK is “L”, be sure to input data for Left channel in left justified with a vacant bit.

When LRCLK is “H”, be sure to input data for Right channel in left justified with a vacant bit.

SDIN data is written into a DAC data register by the falling edge of LRCLK.

64-clock for one-word.

MSB

LSB

MSB

LSB

SCLK

LRCLK

SDIN

Left channel

Right channel

A SDIN bit is sampled by the rising edge of SCLK.

When LRCLK is “H”, be sure to input data for Left channel by right justified.

When LRCLK is “L”, be sure to input data for Right channel by right justified.

SDIN data is written into a DAC data register by the rising edge of LRCLK.

64-clock for one-word.

MODE1(16bit) MODE2(20bit) MODE3(24bit)

MSB

LSB

MSB

LSB

Left channel

Right channel

SCLK

LRCLK

SDIN

A SDIN bit is sampled by the rising edge of SCLK.

When LRCLK is “H”, be sure to input data for Left channel by right justified.

When LRCLK is “L”, be sure to input data for Right channel by right justified.

SDIN data is written into a DAC data register by the rising edge of LRCLK.

64-clock for one-word.