ML145151 datasheet(22/35 Pages) LANSDALE

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ML145158

OUTPUT PINS

PDout

Phase Detector A Output (Pin 5)

This single–ended (three–state) phase detector output pro-

duces a loop–error signal that is used with a loop filter to con-

trol a VCO.

Frequency fV > fR or fV Leading: Negative Pulses

Frequency fV < fR or fV Lagging: Positive Pulses

Frequency fV = fR and Phase Coincidence:

High–Impedance State

φR, φV

Phase Detector B Outputs (Pins 16, 15)

Double–ended phase detector outputs. These outputs can be

combined externally for a loop–error signal. A single–ended

output is also available for this purpose (see PDout).

If frequency fV is greater than fR or if the phase of fV is

leading, then error information is provided by

φV pulsing low.

φR remains essentially high.

If the frequency fV is less than fR or if the phase of fV is

lagging, then error information is provided by

φR pulsing low.

φV remains essentially high.

If the frequency of fV = fR and both are in phase, then both

φV and φR remain high except for a small minimum time peri-

od when both pulse low in phase.

Dual–Modulus Prescaler Control Output (Pin 12)

This output generates a signal by the on–chip control logic

circuitry for controlling an external dual–modulus prescaler.

The MC level is low at the beginning of a count cycle and

remains low until the ÷ A counter has counted down from its

programmed value. At this time, MC goes high and remains

high until the ÷ N counter has counted the rest of the way

down from its programmed value (N – A additional counts

since both ÷ N and ÷ A are counting down during the first por-

tion of the cycle). MC is then set back low, the counters preset

to their respective programmed values, and the above sequence

repeated. This provides for a total programmable divide value

(NT) = N • P + A where P and P + 1 represent the dual–modu-

lus prescaler divide values respectively for high and low modu-

lus control levels, N the number programmed into the ÷ N

counter, and A the number programmed into the ÷ A counter.

Note that when a prescaler is needed, the dual–modulus ver-

sion offers a distinct advantage. The dual–modulus prescaler

allows a higher reference frequency at the phase detector input,

increasing system performance capability, and simplifying the

loop filter design.

fR,fV

R Counter Output, N Counter Output (Pins 13, 3)

Buffered, divided reference and fin frequency outputs. The

fR and fV outputs are connected internally to the ÷ R and ÷ N

counter outputs respectively, allowing the counters to be used

independently, as well as monitoring the phase detector inputs.

Lock Detector Output (Pin 7)

This output is essentially at a high level when the loop is

locked (fR, fV of same phase and frequency), and pulses low

when loop is out of lock.

REFout

Buffered Reference Oscillator Output (Pin 14)

This output can be used as a second local oscillator, refer-

ence oscillator to another frequency synthesizer, or as the sys-

tem clock to a microprocessor controller.

POWER SUPPLY

VDD

Positive Power Supply (Pin 4)

The positive power supply potential. This pin may range

from + 3 to + 9 V with respect to VSS.

VSS

Negative Power Supply (Pin 6)

The most negative supply potential. This pin is usually-

ground.

ML145158

LANSDALE Semiconductor, Inc.

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