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SE555CD Datasheet(PDF) 9 Page - Texas Instruments

Part # SE555CD
Description  PRECISION TIMERS SE555C FROM TI IS NOT RECOMMENDED FOR NEW DESIGNS
PDF  15 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SE555CD Datasheet(HTML) 9 Page - Texas Instruments

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SLFS022 – D1669, SEPTEMBER 1973—REVISED FEBRUARY 1992
NE555, SA555, SE555, SE555C
PRECISION TIMERS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
APPLICATION INFORMATION
monostable operation
For monostable operation, any of these timers may be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to TRIG sets the flip-flop (Q goes low), drives the output high, and turns
off Q1. Capacitor C is then charged through RA until the voltage across the capacitor reaches the threshold
voltage of THRES input. If TRIG has returned to a high level, the output of the threshold comparator will reset
the flip-flop (Q goes high), drive the output low, and discharge C through Q1.
VCC
(5 V to 15 V)
RA
RL
Output
GND
OUT
VCC
CONT
RESET
DISCH
THRES
TRIG
Input
Time – 0.1 ms/div
Capacitor Voltage
Output Voltage
Input Voltage
RA = 9.1 kΩ
CL = 0.01 µF
RL = 1 kΩ
See Figure 9
5
8
4
7
6
2
3
1
Pin numbers shown are for the D, JG, and P packages.
Figure 9. Circuit for Monostable Operation
Figure 10. Typical Monostable Waveforms
Monostable operation is initiated when TRIG
voltage falls below the trigger threshold. Once
initiated, the sequence ends only if TRIG is high at
the end of the timing interval. Because of the
threshold level and saturation voltage of Q1,
the output pulse duration is approximately
tw = 1.1RAC. Figure 11 is a plot of the time
constant for various values of RA and C. The
threshold levels and charge rates are both directly
proportional to the supply voltage, VCC. The timing
interval is therefore independent of the supply
voltage, so long as the supply voltage is constant
during the time interval.
Applying
a
negative-going
trigger
pulse
simultaneously to RESET and TRIG during the
timing interval discharges C and re-initiates the
cycle, commencing on the positive edge of the
reset pulse. The output is held low as long as the
reset pulse is low. To prevent false triggering,
when RESET is not used, it should be connected
to VCC.
C – Capacitance –
µF
10
1
10–1
10–2
10–3
10–4
100
10
1
0.1
0.01
10–5
0.001
Figure 11. Output Pulse Duration vs Capacitance
RA = 10 MΩ
RA = 10 kΩ
RA = 1 kΩ
RA = 100 kΩ
RA = 1 MΩ



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