TLC976C

10-BIT, 20 MSPS, AREA CCD SIGNAL PROCESSOR

SLAS193 – OCTOBER 1998

11

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

CDS/AGC signal processor

The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled

and held during both the reset reference interval and the video signal interval. By subtracting two resulting

voltage levels, the CDS removes low frequency noise from the output of the CCD sensor. Two sample/hold

control pulses (SHR and SHV) are required to perform the CDS function.

The CCD output is capacitively coupled to the TLC976. The AC coupling capacitor is clamped to establish

proper dc bias during the dummy pixel interval by the CLP2 input. The bias at the input to the TLC976 is set

The signal is sent to AGC after the CDS function is complete. The AGC gain can be adjusted from 5 dB to 39

dB by applying variable dc voltage from 0 V to 3 V at the AGCGAIN terminal.

A low-pass filter is installed at the AGC output to improve signal-to-noise ratio. After its output settles, it is

sampled and held by the SH-PULSE input for digitization. The SH-PULSE should synchronize with the ADC

clock.

The basic black level reference is established by clamping the AGC output to 1.66 V internally by the OBCLP

input during the optical black pixel period. A capacitor of 0.1

µF should be connected to the AGCCLP pin.

To prevent the black level from falling below the basic black level (1.66 V) during the blanking period, the AGC

output level is kept at 1.66 V by the BLK PULSE input. It is recommended that the BLK PULSE be kept low during

the entire blanking period.

The DRV block drives the ADC and adjusts the signal offset at the DRIVE OUT output. The offset can be

adjusted from –450 mV to 550 mV by applying control voltage on the OFFSET pin.

The VRT (3.5 V) and VRB (1.5 V) outputs provide voltage references for the ADC. They should be connected

to the VRT-IN and VRB-IN input pins externally.

analog-to-digital converter (ADC)

The A/DC in the TLC976 performs high-speed analog-to-digital conversion with 10-bit resolution using

semi-flash technique. The latency of the data output valid is 2.5 clocks.

Table 2. ADC Output Code

INPUT VOLTAGE

STEPS

DIGITAL OUTPUT CODE

INPUT VOLTAGE

STEPS

MSB

LSB

VRT

•

•

•

•

•

•

•

•

•

•

VRB

0

•

•

•

•

511

512

•

•

•

•

1023

1111111111

•

•

•

•

1000000000

0111111111

•

•

•

•

0000000000