LT4293 datasheet(32/39 Pages) AD

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Data Sheet

LTC9101-2B/LTC9102

APPLICATIONS INFORMATION

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Rev. 0 | 32 of 39

Figure 49. Power Supply Configuration with External 3.3V Regulator

High-Speed Data Interface

The communication between the LTC9101-2B and LTC9102s is

through a high-speed data interface over either a proprietary isola-

tion scheme or direct connection scheme. For proper operation,

strict layout guidelines must be met, see High-Speed Data Interface

Layout.

In the proprietary isolation scheme, the LTC9101-2B/LTC9102 chip-

set uses transformers to isolate the LTC9101-2B from one to four

LTC9102s (see Figure 50). In this case, the SDAIN and SDAOUT

pins can be shorted to each other and tied directly to the I2C/

SMBus bus. The transformers should be 10Base-T or 10/100Base-

T with a 1:1 turns ratio. Optimally, the selected transformers do not

have common-mode chokes. These transformers typically provide

1500V of isolation between the LTC9101-2B and the LTC9102s.

Significant BOM cost reductions can be achieved using the propri-

etary isolation scheme.

In the direct connection scheme, the LTC9101-2B/LTC9102 chip-

set relies on pre-existing system isolation. In this scheme, the

LTC9101-2B connects directly to one or more LTC9102s using a

proprietary communication protocol (see Figure 51).

External MOSFET

Careful selection of the power MOSFET is critical to system reliabil-

ity. Choosing a MOSFET requires extensive analysis and testing

of the MOSFET SOA curve against the various PSE current limit

conditions. Analog Devices recommends the PSMN075-100MSE,

PSMN040-100MSE, or FDMC3612 for 802.3bt 2-pair applications

up to Class 4 (30W) output power. These MOSFETs are selected

for their proven reliability in PoE applications. Contact Analog

Devices Technical Support before using a MOSFET other than one

of these recommended parts.

Sense Resistors

The LTC9101-2B/LTC9102 is designed for a low 0.1Ω current

sense resistance per channel, laid out as shown in the Layout

Requirements section, Figure 53. In order to meet the IHOLD-2P,

and ILIM-2P accuracy required by the IEEE specification, the sense

resistors should have ±1% tolerance or better, and no more than

±200ppm/°C temperature coefficient.

Port Output Cap

Each port requires a 0.1μF cap across OUTn to AGND (see Figure

52) to keep the LTC9102 stable while in current limit during startup

or overload. Common ceramic capacitors often have significant

voltage coefficients; this means the capacitance is reduced as the

applied voltage increases. To minimize this problem, X7R ceramic

capacitors rated for at least 100V are recommended and must be

located close to the LTC9102.

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