LT4293 datasheet(17/39 Pages) AD

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Data Sheet

LTC9101-2B/LTC9102

PIN FUNCTIONS

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Rev. 0 | 17 of 39

Pin No.

Mnemonic

Description

Pin 2

EXT3

External 3.3V Enable. Connect the

EXT3 pin to CAP3 to shut off the

internal 3.3V regulator when power is

supplied externally. Float or connect to

VEE for internal regulator operation.

Pins 47, 46, 39, 38,

31, 30, 23, 22, 15,

14, 7, 6

Respectively

VSSK[12:1]

Kelvin Sense to VEE. Connect to VEE

side of sense resistor for channel n

through a 0.1Ω resistor. Do not connect

directly to VEE plane. See the Kelvin

Sense section for requirements.

Pins 48, 45, 40, 37,

32, 29, 24, 21, 16,

13, 8, 5

Respectively

SENSE[12:1]

Current Sense Input, channel n.

SENSEn monitors the external

MOSFET current via a 0.1Ω sense

resistor between SENSEn and VSSKn.

If the voltage across the sense resistor

reaches the current limit threshold

ILIM-2P, the GATEn pin voltage is

lowered to maintain constant current

in the external MOSFET. See the

Applications Information section for

additional details. If the channel is

unused, tie SENSEn to VEE.

Pins 49, 44, 41, 36,

33, 28, 25, 20, 17,

12, 9, 4

Respectively

OUT[12:1]

Output Voltage Monitor, channel n.

Connect OUTn to the output channel.

A current limit foldback circuit limits

the power dissipation in the external

MOSFET by reducing the current limit

threshold when the drain-to-source

voltage exceeds 10V. A port power

good event is raised when the voltage

from OUTn to VEE drops below 2.4V

(typ). A 500k resistor is connected

internally from OUTn to AGND when the

channel is idle. If the channel is unused,

the OUTn pin must float.

Pins 50, 43, 42, 35,

34, 27, 26, 19, 18,

11, 10, 3

Respectively

GATE[12:1]

Gate Drive, channel n. Connect GATEn

to the gate of the external MOSFET

for channel n. When the MOSFET is

turned on, the gate voltage is driven to

12V (typ) above VEE. During a current

limit condition, the voltage at GATEn

will be reduced to maintain constant

current through the external MOSFET.

If the fault timer expires, GATEn is

pulled down, turning the MOSFET off

and raising a port fault event. If the

channel is unused, the GATEn pin must

float.

Pins 52, 51

Respectively

ID[1:0]

Transceiver ID. Sets the address of the

LTC9102 on the multidrop high-speed

data interface. ID numbering must start

at 00b. Tie high by connecting to CAP3.

Tie low by connecting to VEE. See

the Device Configuration section for

additional details.

Pin 55

PWRIN

Startup Regulator Bypass and External

Low Voltage Supply Input. Power for the

Pin No.

Mnemonic

Description

internal 4.3V and 3.3V internal supplies.

An internal regulator maintains the

voltage of this pin above 6V. An external

resistor or supply may be connected

to this node to improve the power

efficiency of the LTC9102. Connect a

1µF capacitor between this pin and VEE.

Pin 56

AGND

Analog Ground.

Pins 57, 58

Respectively

PWRMD[1:0]

Maximum Power Mode Input. Connect

PWRMD0 of the LTC9102 with ID[1:0] =

00b to VEE with configuration resistor

RPWRMD. When the LTC9101-2B is

reset, RPWRMD selects initial maximum

power allocation values for every port

in the chipset; the system power

supply must be sized to support all

ports outputting up to RPWRMD. When

auto mode is enabled, the chipset

runs independently as a PoE PSE.

The chipset detects and classes all

ports, granting power to each port

up to RPWRMD setting. The PWRMD0

pin of LTC9102 with ID pins set

to 01b, 10b, and 11b must be left

floating. The PWRMD1 pin of all

LTC9102 must be left floating. See

the Auto Mode Maximum PSE Power

section for RPWRMD options and details.

The PWRMD pins are ignored when

a custom configuration package is

present. See the Stored Configurations

section for additional details.

Pin 59

CAP4

Analog Internal 4.3V Power Supply

Bypass Capacitor. Connect a 1μF

ceramic cap to VEE. Do not source or

sink current from this pin.

Pins 60, 65

VEE

Main PoE Supply Input. Connect to a

–51V to –57V supply, relative to AGND.

Voltage depends on PSE Type (Type 3

or 4).

Pin 61

DNA

Data Transceiver Negative Input Output

(Analog). Connect to DND through a

data transformer.

Pin 62

DPA

Data Transceiver Positive Input Output

(Analog). Connect to DPD through a

data transformer.

Pin 63

CNA

Clock Transceiver Negative Input

Output (Analog). Connect to CND

through a data transformer.

Pin 64

CPA

Clock Transceiver Positive Input Output

(Analog). Connect to CPD through a

data transformer.

Common Pins

LTC9101-2B Pins

4, 13; LTC9102

Pins 53, 54

NC, DNC

All pins identified with “NC” or “DNC”

must be left unconnected.

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