LT4293 datasheet(30/39 Pages) AD

30 / 39 page

Data Sheet

LTC9101-2B/LTC9102

APPLICATIONS INFORMATION

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Two complete copies of the firmware image are maintained under

separate ECC and CRC protection for maximum data protection.

Stored Configurations

Custom I2C register map initial values may optionally be stored in

a dedicated flash partition (configuration package). When shipped

from the factory, the LTC9101-2B contains a default configuration

package where register map initial values are as specified in the

LTC9101-2B Software Interface guide. Register map default config-

urations may be stored during manufacturing bring up or field-up-

dated via configuration package download and will be auto-loaded

at boot.

Contact ADI applications support for assistance in generating

custom configuration packages. Configuration packages are down-

loaded using the same code download mechanisms as firmware

packages. Package headers ensure configuration packages are

verified and stored in the appropriate flash partition.

With a configuration package, the user may override the PWRMD0

pin and specify the maximum power level for each port. The user

may override the AD[4:1] pins and specify the I2C chip addresses of

each quad. The CFG[1:0] pins are still required to be set, as these

pins inform the LTC9101-2B how many LTC9102s are attached.

Two identical copies of the configuration image are maintained un-

der separate ECC and CRC protection for maximum data integrity.

SERIAL DIGITAL INTERFACE

Overview

The LTC9101-2B communicates with the host using a standard

SMBus/I2C 2-wire interface. The LTC9101-2B is a subordinate

device, and communicates with the host controller using standard

SMBus protocols. Interrupts are signaled to the host via INT. The

timing diagrams (Figure 31 through Figure 35) show typical commu-

nication waveforms and their timing relationships. More information

about the SMBus data protocols can be found at www.smbus.org.

Bus Addressing

The LTC9101-2B’s primary 7-bit serial bus address is

01A4A3A2A10b, with bits 4:1 set by AD[4:1] respectively. See Table

8 for device configuration options. Depending on device configura-

tion, up to 12 I2C addresses will be populated from the I2C base

address upwards. All LTC9101-2Bs also respond to the broadcast

address 1111111b, allowing the host to write the same command

(typically configuration commands) to multiple LTC9101-2Bs in a

single transaction. If the LTC9101-2B is asserting INT, it will also

respond to the alert response address (0001100b) per the SMBus

specification.

Each LTC9101-2B/LTC9102 is logically composed of multiple four

port groups, known as quads, each packed into a single I2C

address. See the Device Configuration section for details. For

example, if CFG[1:0] is set to 00, an LTC9101-2B is configured as

a 12-port device when attached to an LTC9102 (see Table 8). This

configuration requires consecutive I2C addresses, with quad offset

0 starting at the I2C base address.

Interrupts and SMBAlert

Most port events can be configured to trigger an interrupt, asserting

INT and alerting the host to the event. This removes the need for

the host to poll the LTC9101-2B, minimizing serial bus traffic and

conserving host CPU cycles. Multiple LTC9101-2Bs can share a

common INT line, with the host using the SMBAlert protocol (ARA)

to determine which LTC9101-2B caused an interrupt.

For information on serial bus usage and device configuration and

status, refer to the LTC9101-2B Software Interface guide. To re-

quest the Software Interface guide, please complete the Software

Request Form.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network segments

(including PoE circuitry) be electrically isolated from the chassis

ground of each network interface device. However, network seg-

ments are not required to be isolated from each other, provided

that the segments are connected to devices residing within a single

building on a single power distribution system.

If the PSE is part of a larger system, contains additional external

non-Ethernet ports, or must be referenced to protective ground for

some other reason, the PoE subsystem must be electrically isolated

from the rest of the system.

The LTC9101-2B/LTC9102 chipset simplifies PSE isolation by al-

lowing the LTC9101-2B chip to reside on the non-isolated side.

There it can receive power from the main logic supply and con-

nect directly to the I2C/SMBus bus. In this case, the SDAIN and

SDAOUT pins can be tied together and will act as a standard I2C/

SMBus SDA pin. Isolation between the LTC9101-2B and LTC9102

is implemented using a proprietary transformer-based communica-

tion protocol. Additional details are provided in the High-Speed

Data Interface section of this data sheet.

For simple devices, such as unmanaged PoE switches, the isola-

tion requirement can be met by using an isolated main power

supply for the entire device. This strategy can be used if the

device has no electrically conducting ports other than twisted-pair

Ethernet. The LTC9101-2B may directly connect to the LTC9102s

in the above circumstances, or if the system already provides

isolation.

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