DS3102 datasheet(19/141 Pages) MAXIM

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____________________________________________________________________________________________ DS3102

Rev: 102607

19 of 141

00h to indicate the failure. In response to the activation of the INTREQ pin or during periodic polling, if system

software ever reads 00h from the ID registers (which are hard-coded to 0C1Eh = 3102 decimal), it can conclude

that the local oscillator attached to that DS3102 has failed. For proper operation of the watchdog timer, connect the

WDT pin to a 10k

Ω resistor (R) to VDDIO and a 0.01μF capacitor (C) to VSS.

7.4

Input Clock Configuration

The DS3102 has eight input clocks: IC1 to IC6, IC8, and IC9. Table 7-2 provides summary information about each

clock, including signal format and available frequencies. The device tolerates a wide range of duty cycles on input

clocks, out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller.

7.4.1 Signal Format Configuration

Inputs with CMOS/TTL signal format accept both TTL and 3.3V CMOS levels. One key configuration bit that affects

the available frequencies is the SONSDH bit in MCR3. When SONSDH = 1 (SONET mode), the 1.544MHz

frequency is available. When SONSDH = 0 (SDH mode), the 2.048MHz frequency is available. During reset the

default value of this bit is latched from the SONSDH pin.

Input clocks IC1, IC2, IC5, and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using

the proper set of external components. The recommended LVDS termination is shown in Figure 10-1 while the

recommended LVPECL termination is shown in Figure 10-2. The electrical specifications for these inputs are listed

in Table 10-4. To configure these differential inputs to accept single-ended CMOS/TTL signals, use a voltage-

divider to bias the ICxNEG pin to approximately 1.4V and connect the single-ended signal to the ICxPOS pin. If a

differential input is not used it should be configured left floating (one input is internally pulled high and the other

internally pulled low). (See also MCR5:IC5SF and IC6SF.)

Table 7-2. Input Clock Capabilities

INPUT CLOCK

SIGNAL FORMATS

FREQUENCIES (MHz)

DEFAULT FREQUENCY

IC1

LVDS/LVPECL or CMOS/TTL

Up to 156.25 (2)

8kHz

IC2

LVDS/LVPECL or CMOS/TTL

Up to 156.25 (2)

8kHz

IC3

CMOS/TTL

Up to 125 (1)

8kHz

IC4

CMOS/TTL

Up to 125 (1)

8kHz

IC5

LVDS/LVPECL or CMOS/TTL

Up to 156.25 (2)

19.44MHz

IC6

LVDS/LVPECL or CMOS/TTL

Up to 156.25 (2)

19.44MHz

IC8

CMOS/TTL

Up to 125 (1)

19.44MHz

IC9

CMOS/TTL

Up to 125 (1)

19.44MHz

Note 1: Available frequencies for CMOS/TTL input clocks are: 2kHz, 4kHz, 8kHz, 1.544MHz (SONET mode), 2.048MHz (SDH mode),

6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, and any multiple of 2kHz up to 125MHz.

Note 2: Available frequencies for LVDS/LVPECL input clocks include all CMOS/TTL frequencies in Note 1 plus any multiple of 8kHz up to

155.52MHz and 156.25MHz.

DS3102 Datasheet(PDF) 19 Page - Maxim Integrated Products

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