DS3102 datasheet(49/141 Pages) MAXIM

49 / 141 page

____________________________________________________________________________________________ DS3102

Rev: 102607

49 of 141

Control Word. After

CS is pulled low, the bus master transmits the control word during the first 16 SCLK cycles. In

MSB-first mode, the control word has the form:

W A13 A12 A11 A10 A9 A8 A7

A6 A5 A4 A3 A2 A1 A0 BURST

where A[13:0] is the register address, R/

W is the data direction bit (1 = read, 0 = write), and BURST is the burst bit

(1 = burst access, 0 = single-byte access). In LSB-first mode, the order of the 14 address bits is reversed. In the

discussion that follows, a control word with R/

W = 1 is a read control word, while a control word with R/W = 0 is a

write control word.

Single-Byte Writes. See Figure 7-6. After

CS goes low, the bus master transmits a write control word with

BURST = 0 followed by the data byte to be written. The bus master then terminates the transaction by pulling

high.

Single-Byte Reads. See Figure 7-6. After

CS goes low, the bus master transmits a read control word with

BURST = 0. The DS3102 then responds with the requested data byte. The bus master then terminates the

transaction by pulling

CS high.

Burst Writes. See Figure 7-6. After

CS goes low, the bus master transmits a write control word with BURST = 1

followed by the first data byte to be written. The DS3102 receives the first data byte on SDI, writes it to the

specified register, increments its internal address register, and prepares to receive the next data byte. If the master

continues to transmit, the DS3102 continues to write the data received and increment its address counter. After the

address counter reaches 3FFFh it rolls over to address 0000h and continues to increment.

Burst Reads. See Figure 7-6. After

CS goes low, the bus master transmits a read control word with BURST = 1.

The DS3102 then responds with the requested data byte on SDO, increments its address counter, and prefetches

the next data byte. If the bus master continues to demand data, the DS3102 continues to provide the data on SDO,

increment its address counter, and prefetch the following byte. After the address counter reaches 3FFFh, it rolls

over to address 0000h and continues to increment.

Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by

pulling

CS high. In response to early terminations, the DS3102 resets its SPI interface logic and waits for the start

of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data

byte, the data byte is not written.

Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the

DS3102 is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support

this option, the bus master must not drive the SDI/SDO line when the DS3102 is transmitting.

AC Timing. See Table 10-10 and Figure 10-4 for AC timing specifications for the SPI interface.

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