XTPS55285VALR datasheet(21/45 Pages) TI1

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6.5.3 Byte Format

Every byte on the SDA line must be eight bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit

(MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some other

function, it can hold the clock line SCL low to force the controller into a wait state (clock stretching). Data transfer

then continues when the target is ready for another byte of data and release the clock line SCL.

S or Sr

P or Sr

START or

Repeated

START

STOP or

Repeated

START

MSB

Acknowledgement signal

from target

Acknowledgement signal

from receiver

SCL

SDA

Figure 6-7. Byte Format

6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter

that the byte was successfully received and another byte may be sent. All clock pulses, including the

acknowledge 9th clock pulse, are generated by the controller.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line

to low level and it remains stable low level during the high level period of this clock pulse.

The Not Acknowledge signal is when SDA remains high level during the 9th clock pulse. The controller can then

generate either a STOP to abort the transfer or a repeated START to start a new transfer.

6.5.5 Target Address and Data Direction Bit

After the START, a target address is sent. This address is seven bits long followed by the eighth bit as a data

direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

1 - 7

START

SCL

SDA

1 - 7

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

Figure 6-8. Target Address and Data Direction

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TPS55285

SLVSI72 – FEBRUARY 2025

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