ADV3000ASTZ datasheet(12/28 Pages) AD

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ADV3000

Rev. 0 | Page 12 of 28

THEORY OF OPERATION

INTRODUCTION

The primary function of the ADV3000 is to switch one of three

(HDMI or DVI) single-link sources to one output. Each HDMI/

DVI link consists of four differential, high speed channels and

four auxiliary single-ended, low speed control signals. The high

speed channels include a data-word clock and three transition

minimized differential signaling (TMDS) data channels run-

ning at 10× the data-word clock frequency for data rates up to

2.25 Gbps. The four low speed control signals are 5 V tolerant

bidirectional lines that can carry configuration signals, HDCP

encryption, and other information, depending upon the specific

application.

All four high speed TMDS channels in a given link are identical;

that is, the pixel clock can be run on any of the four TMDS

channels. Transmit and receive channel compensation is

provided for the high speed channels where the user can

(manually) select among a number of fixed settings.

The ADV3000 has two control interfaces. Users have the option

of controlling the part through either the parallel control

interface or the I2C serial control interface. The ADV3000 has

two user-programmable I2C slave addresses (one bit) to allow

two ADV3000s to be controlled by a single I2C bus. A RESET

pin is provided to restore the control registers of the ADV3000

to default values. In all cases, serial programming values over-

ride any prior parallel programming values and any use of the

serial control interface disables the parallel control interface

until the ADV3000 is reset.

INPUT CHANNELS

Each high speed input differential pair terminates to the 3.3 V

VTTI power supply through a pair of single-ended 50 Ω on-

chip resistors, as shown in Figure 25. The input terminations

can be optionally disconnected for approximately 100 ms

following a source switch. The user can program which of the

12 high speed input channels employs this feature by selectively

programming the associated RX_PT bits in the input termination

pulse register through the serial control interface. Additionally,

all the input terminations can be disconnected by programming

the RX_TO bit in the receiver settings register. By default, the

input termination is enabled. The input terminations are

enabled and cannot be switched off when programming the

ADV3000 through the parallel control interface.

CABLE

50Ω

IP_xx

IN_xx

AVEE

VTTI

Figure 25. High Speed Input Simplified Schematic

The input equalizer can be manually configured to provide two

different levels of high frequency boost: 6 dB or 12 dB. The user

can individually control the equalization level of all high speed

input channels by selectively programming the associated RX_EQ

bits in the receive equalizer register through the serial control

interface. Alternately, the user can globally control the equaliza-

tion level of all eight high speed input channels by setting the

PP_EQ pin of the parallel control interface. No specific cable

length is suggested for a particular equalization setting because

cable performance varies widely between manufacturers; however,

in general, the equalization of the ADV3000 can be set to 12 dB

without degrading the signal integrity, even for short input

cables. At the 12 dB setting, the ADV3000 can equalize more

than 20 meters of 24 AWG cable at 2.25 Gbps.

OUTPUT CHANNELS

Each high speed output differential pair is terminated to the

3.3 V VTTO power supply through two 50 Ω on-chip resistors

(see Figure 26). This termination is user-selectable; it can be

turned on or off by programming the TX_PTO bit of the

transmitter settings register through the serial control interface.

The output termination resistors of the ADV3000 back-terminate

the output TMDS transmission lines. These back-terminations,

as recommended in the HDMI 1.3 specification, act to absorb

reflections from impedance discontinuities on the output traces,

improving the signal integrity of the output traces and adding

flexibility to how the output traces can be routed. For example,

interlayer vias can be used to route the ADV3000 TMDS outputs

on multiple layers of the PCB without severely degrading the

quality of the output signal.

The ADV3000 output has a disable feature that places the

outputs in an inactive mode. This mode is enabled by

programming the HS_EN bit of the high speed device modes

PP_EN pin of the parallel control interface. Larger wire-OR’ed

arrays can be constructed using the ADV3000 in this mode.

VTTO

50Ω

OPx

ONx

AVEE

DISABLE

IOUT

Figure 26. High Speed Output Simplified Schematic

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