TSL2301

102 × 1 LINEAR OPTICAL SENSOR ARRAY

WITH ANALOGTODIGITAL CONVERTER

TAOS007 – JULY 2000

3

www.taosinc.com

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Copyright

E 2000, TAOS Inc.

Table 1. Gain Settings and Results

GAIN CODE

RELATIVE GAIN

% INCREASE

GAIN CODE

RELATIVE GAIN

% INCREASE

0

1.00

16

1.52

3.23

1

1.02

2.17

17

1.57

3.33

2

1.05

2.22

18

1.62

3.45

3

1.07

2.27

19

1.68

3.57

4

1.09

2.33

20

1.74

3.70

5

1.12

2.38

21

1.81

3.85

6

1.15

2.44

22

1.88

4.00

7

1.18

2.50

23

1.96

4.17

8

1.21

2.56

24

2.05

4.35

9

1.24

2.63

25

2.14

4.55

10

1.27

2.70

26

2.24

4.76

11

1.31

2.78

27

2.35

5.00

12

1.34

2.86

28

2.48

5.26

13

1.38

2.94

29

2.61

5.56

14

1.43

3.03

30

2.77

5.88

15

1.47

3.13

31

2.94

6.25

Register address map

The TSL2301 contains seven registers (Table 2). Three registers control the gain of the analog-to-digital

converters (ADCs). Three other registers allow the offset of the system to be corrected. Together the gain and

offset registers are used to maximize the achievable dynamic range. The last register is a mode register that

selects both device cascade options and production test options. Note that device cascade options do not apply

to the 8-pin packaged device.

Table 2. Register Address Map

ADDRESS

REGISTER DESCRIPTION

REGISTER WIDTH

0

Pixels 0–33 Offset

8

1

Pixels 0–33 Gain

5

2

Pixels 34–67 Offset

8

3

Pixels 34–67 Gain

5

4

Pixels 68–101 Offset

8

5

Pixels 68–101 Gain

5

1F

Mode

4

The offset registers are 8-bit signed offsets and the gain registers are 5-bit magnitudes. The programmed offset

correction is applied to the sampled energy, and then the gain is applied. (e.g., the gain will affect the offset

correction). These two registers allow the user to maximize the dynamic range achievable in the given system.

The mode register is used during factory testing and for future product enhancements. The user should always

program zeros into the mode register.