IL800-Series Isolators

11

NVE Corporation

11409 Valley View Road, Eden Prairie, MN 55344

(952) 829-9217

www.nve.com

www.YouTube.com/NveCorporation

iso-apps@nve.com

Insulation Specifications

Parameters

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Creepage

Distance

(external)

MSOP

QSOP

0.15" SOIC (8 or 16 pin)

0.3" SOIC

3.0

4.03

4.03

8.03

8.3

mm

Per IEC 60601

Total Barrier Thickness (internal)

0.012

0.013

mm

Leakage Current

0.2

µA

240 VRMS, 60 Hz

Barrier Resistance

RIO

>1014

Ω

500 V

Barrier Capacitance

CIO

4

pF

f = 1 MHz

Comparative Tracking Index

CTI

≥175

V

Per IEC 60112

High Voltage Endurance

(Maximum Barrier Voltage

for Indefinite Life)

AC

DC

VIO

1000

1500

VRMS

VDC

At maximum

operating temperature

Barrier Life

44000

Years

100°C, 1000 VRMS, 60%

CL activation energy

Thermal Characteristics

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Junction–Ambient

Thermal Resistance

MSOP8

0.15" SOIC8

QSOP16

0.15" SOIC16

0.3" SOIC16

θ

JA

184

134

100

82

67

°C/W

Double-sided PCB in

free air

Junction–Case (Top)

Thermal Resistance

MSOP8

0.15" SOIC8

QSOP16

0.15" SOIC16

0.3" SOIC16

θ

JC

15

10

9

8

12

Junction–Ambient

Thermal Resistance

0.3" SOIC

θ

JA

46

2s2p PCB in free air

per JESD51

Junction–Case (Top)

Thermal Resistance

θ

JC

9

Power Dissipation

MSOP8

0.15" SOIC8

QSOP16

0.15" SOIC16

0.3" SOIC16

PD

500

675

675

700

1500

mW

Notes:

1.

Absolute maximum means the device will not be damaged if operated under these conditions. It does not guarantee performance.

2.

PWD is defined as |tPHL− tPLH|. %PWD is equal to PWD divided by pulse width.

3.

tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH between devices at 25°C.

4.

CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO> 0.8 VDD2. CML is the maximum common

mode input voltage that can be sustained while maintaining VO< 0.8 V. The common mode voltage slew rates apply to both rising and

falling common mode voltage edges.

5.

Device is considered a two-terminal device: pins on each side of the package are shorted.

6.

Dynamic power consumption is calculated per channel and is supplied by the channel’s input side power supply.

7.

Minimum pulse width is the minimum value at which specified PWD is guaranteed.

8.

The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 12.

9.

External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 12).

10. If internal clock is used, devices will respond to DC states on inputs within a maximum of 9 µs. Outputs may oscillate if the SYNC input slew

rate is less than 1 V/ms.

11. toff is the maximum time for the internal refresh clock to shut down.