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PN511 Datasheet(PDF) 8 Page - NXP Semiconductors

Part # PN511
Description  Transmission Module
PDF  22 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PN511 Datasheet(HTML) 8 Page - NXP Semiconductors

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082733
© NXP B.V. 2007. All rights reserved.
Product short data sheet
Rev. 3.3 — 13 June 2007
8 of 22
NXP Semiconductors
PN511
Transmission Module
7.2 Pin description
Table 3.
Pin description HVQFN32
Symbol
Pin
Type
Description
A1
1
I
Address Line
PVDD
2
PWR
Pad power supply
DVDD
3
PWR
Digital Power Supply
DVSS
4
PWR
Digital Ground
PVSS
5
PWR
Pad power supply ground
NRSTPD
6
I
Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
SIGIN
7
I
Communication Interface Input: accepts a digital, serial data stream
SIGOUT
8
O
Communication Interface Output: delivers a serial data stream
LOADMOD
9
O
Load Modulation Output: provides digital signal for FeliCa and Mifare Card Operation
mode
TVSS
10
PWR
Transmitter Ground: supplies the output stage of TX1 and TX2
TX1
11
O
Transmitter 1: delivers the modulated 13.56 MHz energy carrier
TVDD
12
PWR
Transmitter Power Supply: supplies the output stage of TX1 and TX2
TX2
13
O
Transmitter 2: delivers the modulated 13.56 MHz energy carrier
TVSS
14
PWR
Transmitter Ground: supplies the output stage of TX1 and TX2
AVDD
15
PWR
Analog Power Supply
VMID
16
PWR
Internal Reference Voltage: This pin delivers the internal reference voltage.
RX
17
I
Receiver Input
AVSS
18
PWR
Analog Ground
AUX1
19
O
Auxiliary Outputs: These pins are used for testing.
AUX2
20
O
OSCIN
21
I
Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
OSCOUT
22
O
Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
IRQ
23
O
Interrupt Request: output to signal an interrupt event
ALE
24
I
Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
D1 to D7
25 to 31
I/O
8-bit Bi-directional Data Bus.
Remark: An 8-bit parallel interface is not available.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
A0
32
I
Address Line



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