Analog Integrated Circuit Device Data



Freescale Semiconductor

19

33982

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The 33982 has four operating modes: Sleep, Normal, Fault, and Fail-safe. Table 6 summarizes details contained in succeeding

paragraphs.

SLEEP MODE

The default mode of the 33982 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR), prior to any 

I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused

internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the

device are as if set to logic [0]. The device transitions to the Normal or Fail-safe operating modes based on the WAKE and RST inputs as

defined in Table 6.

NORMAL MODE

The 33982 is in Normal mode when:

•VPWR is within the normal voltage range.

• RST pin is logic [1].

• No fault has occurred.

FAIL-SAFE MODE AND WATCHDOG

If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic [0]

to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance that limits the internal clamp current.

The watchdog timeout is a multiple of an internal oscillator and is specified in Table 15. As long as the WD bit (D7) of an incoming SPI

message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR the device

operates normally. If an internal watchdog timeout occurs before the WD bit, the device reverts to a Fail-safe mode until the device is

reinitialized.

During the Fail-safe mode, the output is ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of

the various direct inputs and modes (Table 7). In this mode, the SPI register content is retained except for overcurrent high and low

detection levels and timing, which are reset to their default value (SOCL, SOCH, OCLT). The watchdog, overvoltage, overtemperature,

and overcurrent circuitry (with default value for this one) are fully operational.

The Fail-safe mode can be detected by monitoring the WDTO bit D2 of the WDR register. This bit is logic [1] when the device is in Fail-

safe mode. The device can be brought out of the Fail-safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or

forcing the FSI pin to logic [0]. Table 6 summarizes the various methods for resetting the device from the latched Fail-safe mode.

Table 6. Fail-safe Operation and Transitions to Other 33982 Modes

Mode

FS

WAKE

RST

WDTO

Comments

Sleep

x

0

0

x

Device is in Sleep mode. All outputs are OFF.

Normal

1

x

1

No

Normal mode. Watchdog is active if enabled.

Fault

0

1

x

No

The device is currently in Fault mode. The faulted output is OFF.

0

x

1

Fail-safe

1

0

1

Yes

Watchdog has timed out and the device is in Fail-safe mode. The output is as configured with the RFS

resistor connected to FSI. RST and WAKE must be transitioned to logic [0] simultaneously to bring the

device out of the Fail-safe mode or momentarily tied the FSI pin to ground.

1

1

1

1

0

1

1

1

0

x = Don’t care.

Table 7. Output State During Fail-safe Mode

RFS (k

)

High-side State

0

Fail-safe Mode Disabled

10

HS OFF

30

HS ON