Analog Integrated Circuit Device Data



Freescale Semiconductor

13

33982

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

TIMING DIAGRAMS

Figure 4. Output Slew Rate and Time Delays

SPI INTERFACE CHARACTERISTICS

tCS

Rising Edge of CS to Falling Edge of CS (Required Setup Time)

–

–

300

ns

(27)

tENBL

Rising Edge of RST to Falling Edge of CS (Required Setup Time)

–

–

5.0

s

(27)

tLEAD

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)

–

50

167

ns

(27)

tWSCLKH

Required High-state Duration of SCLK (Required Setup Time)

–

–

167

ns

(27)

tWSCLKL

Required Low-state Duration of SCLK (Required Setup Time)

–

–

167

ns

(27)

tLAG

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)

–

50

167

ns

(27)

tSI(SU)

SI to Falling Edge of SCLK (Required Setup Time)

–

25

83

ns

(28)

tSI(HOLD)

Falling Edge of SCLK to SI (Required Setup Time)

–

25

83

ns

(28)

tRSO

SO Rise Time

CL = 200 pF

–

25

50

ns

tFSO

SO Fall Time

CL = 200 pF

–

25

50

ns

tRSI

SI, CS, SCLK, Incoming Signal Rise Time

–

–

50

ns

(28)

tFSI

SI, CS, SCLK, Incoming Signal Fall Time

–

–

50

ns

(28)

tSO(EN)

Time from Falling Edge of CS to SO Low-impedance

–

–

145

ns

(29)

tSO(DIS)

Time from Rising Edge of CS to SO High-impedance

–

65

145

ns

(30)

tVALID

Time from Rising Edge of SCLK to SO Data Valid

0.2 VDD SO  0.8 VDD, CL = 200 pF

–

65

105

ns

(31)

Notes

27.

Maximum setup time required for the 33982 is the minimum guaranteed time needed from the microcontroller.

28.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

29.

Time required for output status data to be available for use at SO. 1.0 k

on pull-up on CS.

30.

Time required for output status data to be terminated at SO. 1.0 k

on pull-up on CS.

31.

Time required to obtain valid data out from SO following the rise of SCLK.

Table 5. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 4.5 V

 VDD  5.5 V, 6.0 V  VPWR  27 V, -40C  TA  125C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

Notes

VPWR

VPWR - 0.5V

VPWR - 3V

0.5V

Tdly(off)

SRrA

SRrB

SRfA

SRfB

CS

Tdly(on)

VPWR

VPWR-0.5 V

VPWR-3.5 V

0.5 V

tDLY(ON)

SRRB_SLOW &

SRFB_SLOW & SRFB_FAST

SRFA_SLOW & SRFA_FAST

SRRA_SLOW &

HS

SRRA _FAST

SRRB_FAST

tDLY_SLOW(OFF) & tDLY_FAST(OFF)