Data Sheet

AD7767

SPECIFICATIONS

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Rev. D | 6 of 23

1 Specifications are for all devices, AD7767, AD7767-1, and AD7767-2.

2 See the Terminology section.

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, common-mode input = VREF/2, TA = −40°C (TMIN) to +105°C (TMAX), unless

otherwise noted. Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of

DVDD) and timed from a voltage level of 1.7 V.

Table 3.

Parameter

Limit at tMIN, tMAX

Unit

Description

DRDY OPERATION

t1

510

ns typ

MCLK rising edge to DRDY falling edge

t21

100

ns min

MCLK high pulse width

t31

900

ns max

MCLK low pulse width

t4

265

ns typ

MCLK rising edge to DRDY rising edge (AD7767)

128

ns typ

MCLK rising edge to DRDY rising edge (AD7767-1)

71

ns typ

MCLK rising edge to DRDY rising edge (AD7767-2)

t5

294

ns typ

DRDY pulse width (AD7767)

435

ns typ

DRDY pulse width (AD7767-1)

492

ns typ

DRDY pulse width (AD7767-2)

tREAD2

tDRDY − t5

ns typ

DRDY low period, read data during this period

tDRDY2

n × 8 × tMCLK

ns typ

DRDY period

Read OPERATION

t6

0

ns min

DRDY falling edge to CS setup time

t7

6

ns max

CS falling edge to SDO tristate disabled

t8

60

ns max

Data access time after SCLK falling edge (VDRIVE = 1.7 V)

50

ns max

Data access time after SCLK falling edge (VDRIVE = 2.3 V)

25

ns max

Data access time after SCLK falling edge (VDRIVE = 2.7 V)

24

ns max

Data access time after SCLK falling edge (VDRIVE = 3.0 V)

t9

10

ns min

SCLK falling edge to data valid hold time (VDRIVE = 3.6 V)

t10

10

ns min

SCLK high pulse width

t11

10

ns min

SCLK low pulse width

tSCLK

1/t8

sec min

Minimum SCLK period

t12

6

ns max

Bus relinquish time after CS rising edge

t13

0

ns min

CS rising edge to DRDY rising edge

Read OPERATION WITH CS LOW

t14

0

ns min

DRDY falling edge to data valid setup time

t15

0

ns max

DRDY rising edge to data valid hold time

DAISY-CHAIN OPERATION

t16

1

ns min

SDI valid to SCLK falling edge setup time

t17

2

ns max

SCLK falling edge to SDI valid hold time

SYNC/PD OPERATION

t18

1

ns typ

SYNC/PD falling edge to MCLK rising edge

t19

20

ns typ

MCLK rising edge to DRDY rising edge going into SYNC/PD mode

t20

1

ns min

SYNC/PD rising edge to MCLK rising edge

t21

510

ns typ

MCLK rising edge to DRDY falling edge coming out of SYNC/PD mode

tSETTLING2

590

tMCLK

Filter settling time after a reset or power-down (AD7767)

1180

tMCLK

Filter settling time after a reset or power-down (AD7767-1)

2357

tMCLK

Filter settling time after a reset or power-down (AD7767-2)