®

DDC101

4

SECTION 2

SPECIFICATIONS

ELECTRICAL

All specifications with unipolar current input range, T

INT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC,

unless otherwise noted.

DDC101

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

INPUTS

Charge Input(6)

Unipolar Input Range

BTC Output Code

–1.95

500

pC/Integration

Bipolar Input Range

BTC Output Code

–251.95

250

pC/Integration

Input Current

Unipolar or Bipolar Range

7.8

µA

Current Input Range Examples(10)

Unipolar Input Range

T

INT

= 100

µs

–0.0195

5

µA

Unipolar Input Range

T

INT = 1ms

–1.95

500

nA

Bipolar Input Range

T

INT = 100µs

–2.5195

2.5

µA

Bipolar Input Range

T

INT = 1ms

–251.95

250

nA

Voltage Input Examples(10)

Unipolar Input Range(2)

R

IN

= 10M

Ω, T

INT

= 1ms

–0.0195

5

V

Bipolar Input Range(2)

R

IN = 10MΩ, TINT = 1ms

–2.5195

2.5

V

DYNAMIC CHARACTERISTICS

Conversion Time

64

256 x 106

µs

Integration Time

64

106

µs

System Clock Input

0.5

2

MHz

ACCURACY

Unipolar Mode Noise

Noise, Low Level Current Input(1)

C

SENSOR = 0pF, L = 8

0.9

ppm of FSR, rms(3)

Noise, Low Level Current Input(1)

C

SENSOR = 0pF, L = 1

1.6

ppm of FSR, rms

Noise, Low Level Current Input(1)

C

SENSOR

= 100pF, L = 1

2.1

3

ppm of FSR, rms

Noise, Low Level Current Input(1)

C

SENSOR = 500pF, L = 1

4.2

ppm of FSR, rms

Noise, Voltage Input(1, 2)

R

IN ≥ 20MΩ

1.9

ppm of FSR, rms

Differential Linearity Error

Unipolar Input Range

Entire Range

±0.005% Reading ±0.5ppm FSR, max

0.1% FSR Input

±0.00006

% of FSR

1% FSR Input

±0.00010

% of FSR

10% FSR Input

±0.00055

% of FSR

Unipolar or Bipolar Input Range

±0.0015

% of FSR

Integral Linearity Error

Unipolar Input Range(11)

0 to 500 pc/Integration

±0.0244% Reading ±2.5ppm FSR, max

–1.95 to 0 pc/Integration

±0.0244% Reading ±3.0ppm FSR, max

0.1% FSR Input

±0.00028

% of FSR

1% FSR Input

±0.00050

% of FSR

10% FSR Input

±0.0027

% of FSR

Unipolar or Bipolar Input Range(11)

±0.003

% of FSR

No Missing Codes

Unipolar Input Range

18

Bits

Bipolar Input Range

16

Bits

Input Bias Current

T

A

= +25

°C3

10

pA

DC Gain Error

±0.5

±2

% of FSR

Output Offset Error(8)

±0.5

ppm of FSR

Input Offset Voltage(8)

±0.5

±2mV

External Voltage Reference, V

REF

–2.5

VDC

Internal Test Signal

100

nA

Internal Test Signal Accuracy

±20

nA

Gain Sensitivity to V

REF

V

REF = 2.5V ±0.1V

1:1

PSRR

80

90

dB

PERFORMANCE OVER TEMPERATURE

Output Offset Drift(8)

not including bias current drift

0

µV/°C

Input Offset Voltage Drift(8)

1

µV/°C

Input Bias Current Drift

+25

°C to +45°C

0.1

0.5

pA/

°C

Input Bias Current

T

A

= +85

°C8

40

pA

Gain Drift(4)

±15

ppm/

°C

DIGITAL INPUT/OUTPUT

Logic Family

TTL Compatible CMOS

Logic Level: V

IH

I

IH = +5µA

+2.0

+V

CC

V

V

IL

I

IL = +5µA

–0.3

+0.8

V

V

OH

I

OH = 2 TTL Loads

+2.4

+V

CC

V

V

OL

I

OL

= 2 TTL Loads

0.0

0.4

V

Data Clock

Data I/O

8

MHz

SETUP Code I/O(9)

4

MHz

Data Format

Straight Binary

Unipolar or Bipolar Range

20

Bits

Two’s Complement

Unipolar or Bipolar Range

21

Bits