DDC101 datasheet(8/30 Pages) TI2

8 / 30 page

DDC101

FIGURE 6. DATA TRANSMIT Timing Diagram.

FIGURE 4. Conversion Timing Diagrams.

Input

Range

Output

Format

SETUP In

DATA CLOCK

(4MHz, max for setup)

ACQ

LSB

RESET SETUP In

ACQ

MSB

Read

FIGURE 5. Input/Output Timing Diagram—SETUP Timing Diagram.

SYSTEM

CLOCK

DATA VALID

Out

DATA TRANSMIT

DATA OUTPUT

DATA CLOCK

(8MHz, max for data)

DDC(1)

Bit 1, MSB

DDC(n)

Bit 21, LSB

DDC

(n+1)

Bit 1

Output Disabled

Last DDC

Bit 21

Output Enabled

Output Disabled

Data can be read on rising or falling edge of Data Clock

DATA TRANSMIT In resets DATA VALID Out.

Continuous Integration Timing

Non-Continuous Integration Timing

SYSTEM

CLOCK

FDS In

Internal

Oversampling

Interval

Internal

Reset

SYSTEM

CLOCK

FDS In

Internal

Oversampling

Interval

Internal

Reset

FDS In should be coincident with negative clock.

FDS initiates oversampling period.

M Clock Periods

End of oversample period

initiates reset for next integration.

FDS In should be coincident with negative clock.

FDS initiates oversampling period.

End of FDS In

initiates end of Internal Reset.

End of oversample

period initiates

reset.

When Internal Reset period ends,

next integration begins.

DATA VALID

Out

DATA VALID Out

Next integration begins when 1 clock

period wide Internal Reset ends.

M Clock Periods

INT'

INT

DDC101 Datasheet(PDF) 8 Page - Texas Instruments

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