DIR9001

SLES198A – DECEMBER 2006 – REVISED MAY 2015

www.ti.com

Electrical Characteristics (continued)

All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fS = 96 kHz, PLL locked, XTI connected

6

8.3

mA

to DGND

IDD

Supply current(7)

fS = 96 kHz, PLL locked, XTI connected

9

12.4

mA

to 24.576-MHz resonator

RXIN = H or L, XTI = L, RST = L

72

μA

fS = 96 kHz, PLL locked, XTI connected

40

55

mW

to DGND

PD

Power dissipation (7)

fS = 96 kHz, PLL locked, XTI connected

50

68

mW

to 24.576-MHz resonator

RXIN = H or L, XTI = L, RST = L

0.67

mW

TEMPERATURE RANGE

TA

Operation temperature range

–40

85

°C

θJA

Thermal resistance

28-pin T-SSOP

105

°C/W

7.6 Timing Requirements

All specifications at TA = 25°C, VDD = VCC = 3.3 V (unless otherwise noted)

MIN

NOM

MAX

UNIT

BIPHASE SIGNAL INPUT AND PLL

Input sampling frequency range

28

108

kHz

XTI SOURCE CLOCK

XTI is connected to clock source

24.576

XTI source clock frequency

MHz

XTI is connected to DGND

Not required

XTI input-clock duty cycle

XTI is connected to clock source

45%

55%

CLKST

tCLKST

CLKST pulse duration, high

4

20

μs

LATENCY

tLATE

LRCKO/DOUT latency

See Figure 14

3/fS

s

DATA OUTPUT(1)

tSCY

System clock pulse cycle time

18

ns

Delay time of SCK rising edge to BCK rising

tSCBC

4

8

15

ns

edge

tCKLR

Delay time of BCKO falling edge to LRCKO valid

–5

0.5

0.5

ns

See Figure 16

tBCY

BCKO pulse cycle time

1/64fS

s

tBCH

BCKO pulse duration, HIGH

60

ns

tBCL

BCKO pulse duration, LOW

60

ns

tBCDO

Delay time of BCKO falling edge to DOUT valid

–5

1

5

ns

tr

Rising time of all signals

10

ns

tf

Falling time of all signals

10

ns

(1)

Load capacitance of the LRCKO, BCKO, and DOUT pins is 20 pF. DOUT, LRCKO, and BCKO are synchronized with SCKO.

8

Submit Documentation Feedback

Copyright © 2006–2015, Texas Instruments Incorporated

Product Folder Links: DIR9001