DAC2932 datasheet(21/29 Pages) TI2

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DAC2932

SBAS279D − AUGUST 2003 − REVISED JULY 2005

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Alternatively, bringing GSET low (that is, connected to

AGND), switches the DAC2932 into the simultaneous gain

set mode. Now the full-scale output current of both DAC

channels is determined by only one external RSET resistor

connected to the FSA1 pin. The resistor at the FSA2 pin

may be removed; however, this is not required since this

pin is not functional in this mode and the resistor has no

effect on the gain equation. The formula for deriving the

correct RSET remains unchanged. For example,

RSET = 19.6kΩ will result in a 2mA output for both DACs.

The DAC2932 is specified with GSET being high and

operating in inpendent gain mode. It should be noted that

when using the simultaneous gain mode, the gain error

and gain matching error will increase.

EXTERNAL REFERENCE OPERATION

The internal reference can be disabled by simply applying

an external reference voltage into the REFIN pin, which in

this case functions as an input, as shown in Figure 38. The

use of an external reference may be considered for

applications that require higher accuracy and drift

performance.

RSET

External

Reference

IREF =

VREF

RSET

DAC2932

+1.22V Ref.

FSA

+3V

+VA

REFIN

Current

Sources

Ref

Control

Amp

Figure 38. External Reference Configuration

While a 0.1μF capacitor is recommended for use with the

internal reference, it is optional for the external reference

operation. The reference input, REFIN, has a high input

impedance and can easily be driven by various sources.

V−DAC

The architecture consists of a resistor string DAC followed

by an output buffer amplifier. Figure 39 shows a block

diagram of the DAC architecture.

DAC Register

REF (+)

Resistor

String

REF(

−)

Output

Amplifier

GND

REFV

(+VDV)

VOUT

Figure 39. V-DAC Architecture

The input coding to the V-DAC is straight binary, so the

ideal output voltage is given by:

VOUT + REFV

4096

where D = decimal equivalent of the binary code that is

loaded to the DAC register; it can range from 0 to 4095.

SERIAL INTERFACE

The V−DACs have a three-wire serial interface (SYNC,

SCLK, and DIN), which is compatible with SPI, QSPI, and

Microwire interface standards as well as most Digital

Signal Processors (DSPs).

The write sequence begins by bringing the SYNC line low.

Data from the DIN line is clocked into the 16-bit shift

frequency can be as high as 20MHz, making the V-DACs

compatible with high-speed DSPs. On the 16th falling

edge of the serial clock, the last data bit is clocked in and

the programmed function is executed (that is, a change in

DAC register contents and/or a change in the mode of

operation).

At this point, the SYNC line may be kept low or brought

high. In either case, it must be brought high for a minimum

of 50ns before the next write sequence so that a falling

edge of SYNC can initiate the next write sequence. Since

the SYNC buffer draws more current when the SYNC

signal is high than it does when it is low, SYNC should be

idled low between write sequences for lowest power

operation of the part. As mentioned above, however, it

must be brought high again just before the next write

sequence.

(11)

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