LM3532 datasheet(43/52 Pages) TI2

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LM3532

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SNVS653E – JULY 2011 – REVISED AUGUST 2015

Layout Guidelines (continued)

The following lists the main (layout sensitive) areas of the LM3532 in order of decreasing importance:

Output Capacitor

•

Schottky Cathode to COUT+

•

COUT

− to GND

Schottky Diode

•

SW Pin to Schottky Anode

•

Schottky Cathode to COUT+

Inductor

•

SW Node PCB capacitance to other traces

Input Capacitor

•

CIN+ to IN pin

•

CIN

− to GND

10.1.1 Output Capacitor Placement

The output capacitor is in the path of the inductor current discharge current. As a result, COUT sees a high current

step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Typical turnoff/turnon times

are around 5 ns. Any inductance along this series path from the cathode of the diode through COUT and back into

the LM3532's GND pin contributes to voltage spikes (VSPIKE = LPX × dI/dt) at SW and OUT which can potentially

over-voltage the SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close as possible

to the Cathode of the Schottky diode and COUT− must be connected as close as possible to the LM3532's GND

bump. The best placement for COUT is on the same layer as the LM3532 to avoid any vias that add extra series

inductance (see Layout Examples).

10.1.2 Schottky Diode Placement

The Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high

current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any inductance in series with

the diode causes a voltage spike (VSPIKE = LPX × dI/dt) at SW and OUT which can potentially over-voltage the

SW pin, or feed through to VOUT and through the output capacitor and into GND. Connecting the anode of the

diode as close as possible to the SW pin and the cathode of the diode as close as possible to COUT+ reduces

the inductance (LPX) and minimize these voltage spikes (see Layout Examples).

10.1.3 Inductor Placement

The node where the inductor connects to the LM3532’s SW bump has 2 issues. First, a large switched voltage (0

to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively

coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the

input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause

large voltage drops that negatively affect efficiency.

To reduce the capacitively coupled signal from SW into nearby traces, the SW bump to inductor connection must

be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, other nodes need to

be routed away from SW and not directly beneath. This is especially true for high impedance nodes that are

more susceptible to capacitive coupling such as (SCL, SDA, HWEN, PWM, and possibly ASL1 and ALS2). A

GND plane placed directly below SW helps isolate SW and dramatically reduce the capacitance from SW into

nearby traces.

To limit the trace resistance of the VBATT to inductor connection and from the inductor to SW connection, use

short, wide traces (see Layout Examples).

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