LM71

1

2

3

4

5

CS

GND

SI/O

SC

V

+

LM71

1

2

3

4

6

CS

GND

SI/O

SC

V

+

5

GND

2

LM71, LM71-Q1

SNIS125E – MARCH 2004 – REVISED AUGUST 2018

www.ti.com

Product Folder Links: LM71 LM71-Q1

Submit Documentation Feedback

Copyright © 2004–2018, Texas Instruments Incorporated

3.1 Connection Diagram

Figure 1. 5-Pin SOT-23

See Package Number DBV

Figure 2. 6-Pin WSON No Pull-Back

See Package Number NGG0006A

Table 1. PIN DESCRIPTIONS

Label

Pin Number

Function

Typical Connection

SOT-23-5

WSON-6

CS

1

4

Chip Select input

From controller

GND

2

2, 5

Power Supply Ground

Connect all GND Pins to ground

SI/O

3

3

Slave Input/Output - Serial bus bi-directional

data line. Schmitt trigger input.

From and to controller

SC

4

1

Slave Clock - Serial bus clock Schmitt trigger

input line

From controller

V+

5

6

Positive Supply Voltage Input

DC voltage from 2.65V to 5.5V. Bypass with

a 0.1 μF ceramic capacitor.

3.2 Typical Application

Figure 3. COP Microcontroller Interface

3.1 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

3.2 Trademarks

All trademarks are the property of their respective owners.