SC

SO

CS

t5

30%

70%

70%

SC

70%

30%

70%

30%

70%

30%

SO

CS

t3

t2

t4

t4

70%

30%

tf

tr

30%

70%

5

LM71, LM71-Q1

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SNIS125E – MARCH 2004 – REVISED AUGUST 2018

Product Folder Links: LM71 LM71-Q1

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Copyright © 2004–2018, Texas Instruments Incorporated

(1)

The LM71 will operate properly over the V+ supply voltage range of 2.65V to 5.5V.

(2)

Typicals are at TA = 25°C and represent most likely parametric norm.

(3)

Limits are ensured to AOQL (Average Outgoing Quality Level).

SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS

Unless otherwise noted, these specifications apply for V

+ = 2.65V to 3.6V(1); C

L (load capacitance) on output lines = 100 pF

unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless

otherwise noted.

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

Units

(Limit)

t1

SC (Clock) Period

0.16

DC

μs (min)

(max)

t2

CS Low to SC (Clock) High Set-Up Time

100

ns (min)

t3

CS Low to Data Out (SO) Delay

70

ns (max)

t4

SC (Clock) Low to Data Out (SO) Delay

70

ns (max)

t5

CS High to Data Out (SO) TRI-STATE

200

ns (max)

t6

SC (Clock) High to Data In (SI) Hold Time

50

ns (min)

t7

Data In (SI) Set-Up Time to SC (Clock) High

30

ns (min)

tr

SC (Clock) Rise Time

100

ns (max)

tf

SC (Clock) Fall Time

100

ns (max)

Figure 4. Data Output Timing Diagram

Figure 5. TRI-STATE Data Output Timing Diagram