ELECTRICAL CHARACTERISTICS: VS = ±5V

OPA3875

www.ti.com ............................................................................................................................................ SBOS341D – DECEMBER 2006 – REVISED AUGUST 2008

At G = +2, RL = 150Ω, unless otherwise noted.

OPA3875

MIN/MAX OVER

TYP

TEMPERATURE

0°C to

–40°C to

MIN/

TEST

PARAMETER

CONDITIONS

+25°C

+25°C

(2)

70°C

(3)

+85°C

(3)

UNITS

MAX

LEVEL

(1)

AC PERFORMANCE

See Figure 1

Small-Signal Bandwidth

VO = 200mVPP, RL = 150Ω

700

525

515

505

MHz

min

B

Large-Signal Bandwidth

VO = 4VPP, RL = 150Ω

425

390

380

370

MHz

min

B

Bandwidth for 0.1dB Gain Flatness

VO = 200mVPP

150

MHz

typ

C

Maximum Small-Signal Gain

VO = 200mVPP, RL = 150Ω, f = 5MHz

2.0

2.02

2.03

2.05

V/V

max

B

Minimum Small-Signal Gain

VO = 200mVPP, RL = 150Ω, f = 5MHz

2.0

1.98

1.97

1.95

V/V

min

B

SFDR

10MHz, VO = 2VPP, RL = 150Ω

–68

–65

–64

–63

dBc

max

B

Input Voltage Noise

f > 100kHz

6.7

7.0

7.2

7.4

nV/

√Hz

max

B

Input Current Noise

f > 100kHz

3.8

4.2

4.6

4.9

pA/

√Hz

max

B

NTSC Differential Gain

RL = 150Ω

0.025

%

typ

C

NTSC Differential Phase

RL = 150Ω

0.025

°

typ

C

Slew Rate

VO = ±2V

3100

2800

2700

2600

V/

µs

min

B

Rise Time and Fall Time

VO = 0.5V Step

460

ps

typ

C

VO = 1.4V Step

600

ps

typ

C

CHANNEL-TO-CHANNEL PERFORMANCE

Gain Match

Channel to Channel, RL = 150Ω

±0.05

±0.25

±0.3

±0.35

%

max

A

All inputs, RL = 150Ω

±0.1

±0.5

±0.6

±0.7

%

max

A

Output Offset Voltage Mismatch

All three outputs

±3

±9

±10

±12

mV

max

A

All Hostile Crosstalk

f = 50MHz, RL = 150Ω

–50

dB

typ

C

Channel-to-Channel Crosstalk

f = 50MHz, RL = 150Ω

–58

dB

typ

C

CHANNEL AND CHIP-SELECT PERFORMANCE

SEL (Channel Select) Swtiching Time

RL = 150Ω

4

ns

typ

C

EN (Chip Select) Switching Time

Turn On

9

ns

typ

C

Turn Off

60

ns

typ

C

SEL (Channel Select) Switching Glitch

All Inputs to Ground, At Matched Load

40

mVPP

typ

C

EN (Chip-Select) Switching Glitch

All Inputs to Ground, At Matched Load

15

mVPP

typ

C

All Hostile Disable Feedthrough

50MHz, Chip Disabled (EN = High)

–68

dB

typ

C

Maximum Logic 0

EN, SEL

0.8

0.8

0.8

V

max

B

Minimum Logic 1

EN, SEL

2.0

2.0

2.0

V

min

B

EN Logic Input Current

0V to 4.5V

75

100

125

150

µA

max

A

SEL Logic Input Current

0V to 4.5V

160

200

250

300

µA

max

A

DC PERFORMANCE

Output Offset Voltage

RIN = 0Ω, G = +2V/V

±2.5

±14

±15.8

±17

mV

max

A

Average Output Offset Voltage Drift

RIN = 0Ω, G = +2V/V

±50

±50

µV/°C

max

B

Input Bias Current

±5

±18

±19.5

±20.5

µA

max

A

Average Input Bias Current Drift

±40

±40

nA/°C

max

B

Gain Error (from 2V/V)

VO = ±2V

0.4

1.4

1.5

1.6

%

max

A

INPUT

Input Voltage Range

±2.8

V

typ

C

Input Resistance

1.75

M

Ω

typ

C

Input Capacitance

Channel Selected

0.9

pF

typ

C

Channel Deselected

0.9

pF

typ

C

Chip Disabled

0.9

pF

typ

C

(1)

Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization

and simulation. (C) Typical value only for information.

(2)

Junction temperature = ambient for +25°C tested specifications.

(3)

Junction temperature = ambient at low temperature limit; junction temperature = ambient +36°C at high temperature limit for over

temperature specifications.

Copyright © 2006–2008, Texas Instruments Incorporated

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