INTERFACE TIMING REQUIREMENTS

t(MCH)

MS

t(MSS)

LSB

t(MCL)

t(MHH)

t(MSH)

t(MCY)

t(MDH)

t(MDS)

MC

MD

T0013-03

I

2C INTERFACE

SLAVE ADDRESS

PCM1680

SLES133B – MARCH 2005 – REVISED OCTOBER 2008.................................................................................................................................................. www.ti.com

Figure 26 shows a detailed timing diagram for the serial control interface. Special attention to the setup and hold

times is required. Also, t(MSS) and t(MSH), which define minimum delays between edges of the MS and MC clocks,

require special attention. These timing parameters are critical for proper control port operation.

PARAMETER

MIN

UNIT

t(MCY)

MC pulse cycle time

100

ns

t(MCL)

MC pulse duration, LOW

50

ns

t(MCH)

MC pulse duration, HIGH

50

ns

t(MHH)

MS pulse duration, HIGH

(1)

t(MSS)

MS falling edge to MC rising edge

20

ns

t(MSH)

MS hold time, MC rising edge for LSB to MS rising edge

20

ns

t(MDH)

MD hold time

15

ns

t(MDS)

MD setup time

20

ns

(1) 3/(256 fS), fS: sampling rate

Figure 26. Interface Timing

The PCM1680 supports the I2C serial bus and data transmission protocol for standard mode as a slave device.

This protocol is explained in the I2C specification 2.0. The PCM1680 does not support a board-to-board interface.

Figure 27 shows the I2C framework for basic read and write operations.

MSB

LSB

1

0

0

1

1

0

ADR

R/W

The PCM1680 has seven bits for its own slave address. The first six bits (MSBs) of the slave address are factory

preset to 1001 10. The next bit of the address byte is the device select bit, which can be user-defined using the

ADR terminal. A maximum of two PCM1680s can be connected on the same bus at one time. Each PCM1680

responds when it receives its own slave address.

18

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