R0002-02

M: Master Device S: Slave Device St: Start Condition

Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge

W: Write R: Read

Transmitter

M

M

M

S

Data Type

St

Slave Address

W

ACK

M

Reg Address

M

Sr

M

Slave Address

S

ACK

M

R

S

ACK

M

Sp

M

NACK

S

Read Data

TIMING DIAGRAM

SDA

SCL

t(BUF)

t(D-SU)

t(D-HD)

Start

t(LOW)

t(S-HD)

t(SCL-F)

t(SCL-R)

t(HI)

Repeated Start

t(RS-SU)

t(RS-HD)

t(SDA-F)

t(SDA-R)

t(P-SU)

Stop

T0050-01

PCM1680

SLES133B – MARCH 2005 – REVISED OCTOBER 2008.................................................................................................................................................. www.ti.com

NOTE: The slave address after the repeated start condition must be the same as the previous slave address.

Figure 29. Read Operation

PARAMETER

MIN

MAX

UNIT

f(SCL)

SCL clock frequency

100

kHz

t(BUF)

Bus free time between a STOP and START condition

4.7

µs

t(LOW)

Low period of the SCL clock

4.7

µs

t(HI)

High period of the SCL clock

4

µs

t(RS-SU)

Setup time for (repeated) START condition

4.7

µs

t(S-HD)

Hold time for (repeated) START condition

4

µs

t(RS-HD)

t(D-SU)

Data setup time

250

ns

t(D-HD)

Data hold time

0

900

ns

t(SCL-R)

Rise time of SCL signal

20 + 0.1 CB

1000

ns

Rise time of SCL signal after a repeated START condition and after

t(SCL-R1)

20 + 0.1 CB

1000

ns

an acknowledge bit

t(SCL-F)

Fall time of SCL signal

20 + 0.1 CB

1000

ns

t(SDA-R)

Rise time of SDA signal

20 + 0.1 CB

1000

ns

t(SDA-F)

Fall time of SDA signal

20 + 0.1 CB

1000

ns

t(P-SU)

Setup time for STOP condition

4

µs

CB

Capacitive load for SDA and SCL lines

400

pF

Noise margin at high level for each connected device

VNH

0.2 VDD

V

(including hysteresis)

Figure 30. Interface Timing

20

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